RSTMGR Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.550s 251.163us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 0.880s 153.947us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 8.940s 2.274ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 1.870s 161.537us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 1.570s 159.325us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
rstmgr_csr_aliasing 1.870s 161.537us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 0.930s 187.856us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.680s 519.862us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.470s 275.654us 50 50 100.00
V2 reset_info rstmgr_reset 6.820s 1.891ms 50 50 100.00
V2 cpu_info rstmgr_reset 6.820s 1.891ms 50 50 100.00
V2 alert_info rstmgr_reset 6.820s 1.891ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 6.820s 1.891ms 50 50 100.00
V2 stress_all rstmgr_stress_all 54.540s 18.242ms 50 50 100.00
V2 alert_test rstmgr_alert_test 0.800s 89.784us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.740s 577.743us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.740s 577.743us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 0.880s 153.947us 5 5 100.00
rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
rstmgr_csr_aliasing 1.870s 161.537us 5 5 100.00
rstmgr_same_csr_outstanding 1.510s 260.364us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 0.880s 153.947us 5 5 100.00
rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
rstmgr_csr_aliasing 1.870s 161.537us 5 5 100.00
rstmgr_same_csr_outstanding 1.510s 260.364us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.770s 16.511ms 5 5 100.00
rstmgr_tl_intg_err 3.020s 873.574us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.770s 16.511ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.770s 16.511ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.020s 873.574us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.210s 177.656us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 9.040s 2.357ms 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.120s 244.694us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.770s 16.511ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.810s 80.625us 20 20 100.00
V2S TOTAL 175 175 100.00
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 5 100.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.53 99.41 99.31 99.88 -- 99.83 100.00 98.77

Past Results