748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 1.520s | 257.743us | 41 | 50 | 82.00 |
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 0.870s | 145.160us | 5 | 5 | 100.00 |
| V1 | csr_rw | rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 9.840s | 2.298ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rstmgr_csr_aliasing | 1.800s | 156.737us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 1.660s | 170.660us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 |
| rstmgr_csr_aliasing | 1.800s | 156.737us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 95 | 105 | 90.48 | |||
| V2 | reset_stretcher | rstmgr_por_stretcher | 0.950s | 226.697us | 42 | 50 | 84.00 |
| V2 | sw_rst | rstmgr_sw_rst | 2.580s | 485.956us | 37 | 50 | 74.00 |
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 1.330s | 226.209us | 41 | 50 | 82.00 |
| V2 | reset_info | rstmgr_reset | 7.200s | 2.068ms | 43 | 50 | 86.00 |
| V2 | cpu_info | rstmgr_reset | 7.200s | 2.068ms | 43 | 50 | 86.00 |
| V2 | alert_info | rstmgr_reset | 7.200s | 2.068ms | 43 | 50 | 86.00 |
| V2 | reset_info_capture | rstmgr_reset | 7.200s | 2.068ms | 43 | 50 | 86.00 |
| V2 | stress_all | rstmgr_stress_all | 55.640s | 16.495ms | 41 | 50 | 82.00 |
| V2 | alert_test | rstmgr_alert_test | 0.810s | 71.785us | 36 | 50 | 72.00 |
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 3.240s | 590.865us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 3.240s | 590.865us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 0.870s | 145.160us | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 1.800s | 156.737us | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 1.510s | 264.568us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 0.870s | 145.160us | 5 | 5 | 100.00 |
| rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 | ||
| rstmgr_csr_aliasing | 1.800s | 156.737us | 5 | 5 | 100.00 | ||
| rstmgr_same_csr_outstanding | 1.510s | 264.568us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 280 | 340 | 82.35 | |||
| V2S | tl_intg_err | rstmgr_sec_cm | 28.400s | 16.533ms | 4 | 5 | 80.00 |
| rstmgr_tl_intg_err | 3.060s | 891.780us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | rstmgr_sec_cm | 28.400s | 16.533ms | 4 | 5 | 80.00 |
| V2S | prim_fsm_check | rstmgr_sec_cm | 28.400s | 16.533ms | 4 | 5 | 80.00 |
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 3.060s | 891.780us | 20 | 20 | 100.00 |
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 1.200s | 180.947us | 42 | 50 | 84.00 |
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 8.260s | 2.378ms | 42 | 50 | 84.00 |
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 1.180s | 244.457us | 38 | 50 | 76.00 |
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 28.400s | 16.533ms | 4 | 5 | 80.00 |
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 |
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 0.840s | 96.940us | 20 | 20 | 100.00 |
| V2S | TOTAL | 146 | 175 | 83.43 | |||
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 521 | 620 | 84.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 4 | 66.67 |
| V2 | 8 | 8 | 2 | 25.00 |
| V2S | 5 | 5 | 1 | 20.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.44 | 99.40 | 99.31 | 99.88 | -- | 99.83 | 99.46 | 98.77 |
Exit reason: Error: User command failed Job returned non-zero exit code has 99 failures:
Test rstmgr_sec_cm has 1 failures.
2.rstmgr_sec_cm.32660360644635366804727312639610220863796286604515407483841923962797081221770
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest/run.log
[make]: simulate
cd /workspace/2.rstmgr_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612176010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1612176010
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rstmgr_leaf_rst_cnsty has 8 failures.
5.rstmgr_leaf_rst_cnsty.53002933395131336689476296072927760194987868785999668801936801688290589512589
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest/run.log
[make]: simulate
cd /workspace/5.rstmgr_leaf_rst_cnsty/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.23958413
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
13.rstmgr_leaf_rst_cnsty.64938124863951751433311245159034422678345510502922661908980648702751984547819
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest/run.log
[make]: simulate
cd /workspace/13.rstmgr_leaf_rst_cnsty/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016114667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2016114667
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test rstmgr_sw_rst_reset_race has 9 failures.
7.rstmgr_sw_rst_reset_race.63844829282566454115401190725527498721449864205272892223711561419917342345668
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest/run.log
[make]: simulate
cd /workspace/7.rstmgr_sw_rst_reset_race/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193347524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1193347524
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
8.rstmgr_sw_rst_reset_race.64594438567678686814261565966326287678255616701829850083629763613302581803853
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest/run.log
[make]: simulate
cd /workspace/8.rstmgr_sw_rst_reset_race/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320860493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1320860493
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 7 more failures.
Test rstmgr_sec_cm_scan_intersig_mubi has 8 failures.
8.rstmgr_sec_cm_scan_intersig_mubi.107479776792727345594810458489193872267902350585302491169532241504610175077272
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670040472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1670040472
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
19.rstmgr_sec_cm_scan_intersig_mubi.51079141548477013287587978970449149536506747356002804275144998371170524494373
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282022437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4282022437
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test rstmgr_alert_test has 14 failures.
9.rstmgr_alert_test.83642920289031155285442131391623585742582276853590096540660693964831239011710
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_alert_test/latest/run.log
[make]: simulate
cd /workspace/9.rstmgr_alert_test/latest && /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421339006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3421339006
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
14.rstmgr_alert_test.90380775835140670280329450980628185754229851836464306000296984732722328637499
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/14.rstmgr_alert_test/latest/run.log
[make]: simulate
cd /workspace/14.rstmgr_alert_test/latest && /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247074875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.247074875
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 12 more failures.
... and 7 more tests.