042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rstmgr_smoke | 1.560s | 229.697us | 45 | 50 | 90.00 |
| V1 | csr_hw_reset | rstmgr_csr_hw_reset | 0.930s | 154.321us | 4 | 5 | 80.00 |
| V1 | csr_rw | rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | rstmgr_csr_bit_bash | 9.190s | 2.291ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | rstmgr_csr_aliasing | 2.300s | 350.196us | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | 1.790s | 180.902us | 16 | 20 | 80.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 |
| rstmgr_csr_aliasing | 2.300s | 350.196us | 3 | 5 | 60.00 | ||
| V1 | TOTAL | 90 | 105 | 85.71 | |||
| V2 | reset_stretcher | rstmgr_por_stretcher | 0.980s | 222.625us | 44 | 50 | 88.00 |
| V2 | sw_rst | rstmgr_sw_rst | 2.840s | 529.747us | 49 | 50 | 98.00 |
| V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | 1.600s | 298.996us | 42 | 50 | 84.00 |
| V2 | reset_info | rstmgr_reset | 7.860s | 2.093ms | 46 | 50 | 92.00 |
| V2 | cpu_info | rstmgr_reset | 7.860s | 2.093ms | 46 | 50 | 92.00 |
| V2 | alert_info | rstmgr_reset | 7.860s | 2.093ms | 46 | 50 | 92.00 |
| V2 | reset_info_capture | rstmgr_reset | 7.860s | 2.093ms | 46 | 50 | 92.00 |
| V2 | stress_all | rstmgr_stress_all | 53.790s | 14.292ms | 41 | 50 | 82.00 |
| V2 | alert_test | rstmgr_alert_test | 1.010s | 204.289us | 47 | 50 | 94.00 |
| V2 | tl_d_oob_addr_access | rstmgr_tl_errors | 3.480s | 509.959us | 17 | 20 | 85.00 |
| V2 | tl_d_illegal_access | rstmgr_tl_errors | 3.480s | 509.959us | 17 | 20 | 85.00 |
| V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset | 0.930s | 154.321us | 4 | 5 | 80.00 |
| rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 | ||
| rstmgr_csr_aliasing | 2.300s | 350.196us | 3 | 5 | 60.00 | ||
| rstmgr_same_csr_outstanding | 1.490s | 203.029us | 16 | 20 | 80.00 | ||
| V2 | tl_d_partial_access | rstmgr_csr_hw_reset | 0.930s | 154.321us | 4 | 5 | 80.00 |
| rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 | ||
| rstmgr_csr_aliasing | 2.300s | 350.196us | 3 | 5 | 60.00 | ||
| rstmgr_same_csr_outstanding | 1.490s | 203.029us | 16 | 20 | 80.00 | ||
| V2 | TOTAL | 302 | 340 | 88.82 | |||
| V2S | tl_intg_err | rstmgr_sec_cm | 32.790s | 16.521ms | 4 | 5 | 80.00 |
| rstmgr_tl_intg_err | 2.960s | 918.123us | 16 | 20 | 80.00 | ||
| V2S | prim_count_check | rstmgr_sec_cm | 32.790s | 16.521ms | 4 | 5 | 80.00 |
| V2S | prim_fsm_check | rstmgr_sec_cm | 32.790s | 16.521ms | 4 | 5 | 80.00 |
| V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | 2.960s | 918.123us | 16 | 20 | 80.00 |
| V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | 1.230s | 173.494us | 47 | 50 | 94.00 |
| V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | 9.410s | 2.350ms | 47 | 50 | 94.00 |
| V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | 1.140s | 244.280us | 47 | 50 | 94.00 |
| V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | 32.790s | 16.521ms | 4 | 5 | 80.00 |
| V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 |
| V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | 0.920s | 58.697us | 18 | 20 | 90.00 |
| V2S | TOTAL | 161 | 175 | 92.00 | |||
| V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 553 | 620 | 89.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 8 | 8 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.44 | 99.40 | 99.31 | 99.88 | -- | 99.83 | 99.46 | 98.77 |
Exit reason: Error: User command failed Job returned non-zero exit code has 64 failures:
Test rstmgr_sw_rst_reset_race has 8 failures.
0.rstmgr_sw_rst_reset_race.90266750695344132091271434829837768256828002632876416470890836934519573874276
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest/run.log
[make]: simulate
cd /workspace/0.rstmgr_sw_rst_reset_race/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249464420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.249464420
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:56 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.rstmgr_sw_rst_reset_race.92794604262313741143785555365388957752460990558370032006702981976911964037211
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest/run.log
[make]: simulate
cd /workspace/4.rstmgr_sw_rst_reset_race/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738380891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2738380891
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:56 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test rstmgr_sec_cm_scan_intersig_mubi has 3 failures.
0.rstmgr_sec_cm_scan_intersig_mubi.94876390726973501304016105292350006992179600656992350383980503261457809493667
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538005155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.538005155
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.rstmgr_sec_cm_scan_intersig_mubi.72663423775596065819289071768316858628898201675078330753757918010306039934718
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest/run.log
[make]: simulate
cd /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956067582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.956067582
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:56 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test rstmgr_tl_intg_err has 3 failures.
0.rstmgr_tl_intg_err.55997399674936523762693373903693505286644292485856443326251043505977138671122
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/0.rstmgr_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804294674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.3804294674
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.rstmgr_tl_intg_err.73296278489593672759937301163994097339336120025581407257007742774169072436231
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/2.rstmgr_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973893639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2973893639
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test rstmgr_csr_hw_reset has 1 failures.
0.rstmgr_csr_hw_reset.77186410022183026911516906407143917339006479208954901852693496630364548085362
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/0.rstmgr_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999170674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2999170674
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rstmgr_csr_bit_bash has 1 failures.
0.rstmgr_csr_bit_bash.4222824913105878794960240743798823530263190447362635759447358444873917923517
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.rstmgr_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879493309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.879493309
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 14 more tests.
Job rstmgr-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test rstmgr_same_csr_outstanding has 1 failures.
0.rstmgr_same_csr_outstanding.107859866989919390460095123442985996570884304714812182167869095218170454002238
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest/run.log
Job ID: smart:d833ddf4-f66a-4242-ba3c-865f2a1a10f1
Test rstmgr_tl_intg_err has 1 failures.
10.rstmgr_tl_intg_err.28423247855693142802324967635397783730370993505276832509001341638241199588305
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest/run.log
Job ID: smart:75d982d7-65a3-4f48-bb44-1695dd64a682
Test rstmgr_tl_errors has 1 failures.
12.rstmgr_tl_errors.89793099693674796141274826033884288608305061307417861367737946538837968065089
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest/run.log
Job ID: smart:02cd2c20-3b0c-4e9c-9c92-dcaea96635d2