RSTMGR Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: `cf38c1d296`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.610s	252.367us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.130s	147.040us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	9.680s	1.992ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.000s	163.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.700s	166.700us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
		rstmgr_csr_aliasing	2.000s	163.241us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.110s	238.482us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.710s	484.450us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.500s	281.533us	49	50	98.00
V2	reset_info	rstmgr_reset	7.420s	1.910ms	50	50	100.00
V2	cpu_info	rstmgr_reset	7.420s	1.910ms	50	50	100.00
V2	alert_info	rstmgr_reset	7.420s	1.910ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	7.420s	1.910ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	51.600s	15.857ms	49	50	98.00
V2	alert_test	rstmgr_alert_test	0.880s	126.860us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.830s	543.195us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.830s	543.195us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.130s	147.040us	5	5	100.00
		rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
		rstmgr_csr_aliasing	2.000s	163.241us	5	5	100.00
		rstmgr_same_csr_outstanding	1.620s	212.491us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.130s	147.040us	5	5	100.00
		rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
		rstmgr_csr_aliasing	2.000s	163.241us	5	5	100.00
		rstmgr_same_csr_outstanding	1.620s	212.491us	20	20	100.00
V2		TOTAL			338	340	99.41
V2S	tl_intg_err	rstmgr_sec_cm	31.560s	16.524ms	5	5	100.00
		rstmgr_tl_intg_err	4.300s	1.612ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	31.560s	16.524ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	31.560s	16.524ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	4.300s	1.612ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.220s	174.941us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.420s	2.373ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.240s	243.527us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	31.560s	16.524ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.870s	73.705us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			618	620	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	6	75.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.88	--	99.83	99.46	98.77

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test rstmgr_sw_rst_reset_race has 1 failures.

22.rstmgr_sw_rst_reset_race.69101883598535094456109428318146028102611079254131290661611887991292575240329
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest/run.log

  [make]: simulate
  cd /workspace/22.rstmgr_sw_rst_reset_race/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643977353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.643977353
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 10 13:05 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test rstmgr_stress_all has 1 failures.

29.rstmgr_stress_all.72760352056977620875861342524285361728990092828036392768759167678346061721573
Log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/29.rstmgr_stress_all/latest/run.log

  [make]: simulate
  cd /workspace/29.rstmgr_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399449061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2399449061
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 10 12:49 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255