Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_src.u_aon_rst.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_pd_rst.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_pd_rst.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_src.u_aon_rst.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_src.u_aon_rst.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_pd_rst.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_pd_rst.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_sys.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_sys.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic 100.00 100.00 100.00

Line Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%