Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |