Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1332927 |
1300735 |
0 |
0 |
selKnown1 |
188544 |
156352 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1332927 |
1300735 |
0 |
0 |
T1 |
347 |
284 |
0 |
0 |
T2 |
3507 |
3443 |
0 |
0 |
T3 |
504 |
440 |
0 |
0 |
T4 |
64 |
0 |
0 |
0 |
T5 |
136 |
72 |
0 |
0 |
T6 |
64 |
0 |
0 |
0 |
T7 |
3032 |
2968 |
0 |
0 |
T8 |
5853 |
5789 |
0 |
0 |
T9 |
142 |
78 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
283 |
0 |
0 |
T12 |
0 |
605 |
0 |
0 |
T13 |
0 |
39 |
0 |
0 |
T21 |
541 |
34560 |
0 |
0 |
T22 |
0 |
184 |
0 |
0 |
T23 |
0 |
26 |
0 |
0 |
T25 |
0 |
26 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
188544 |
156352 |
0 |
0 |
T1 |
128 |
64 |
0 |
0 |
T2 |
704 |
640 |
0 |
0 |
T3 |
64 |
0 |
0 |
0 |
T4 |
64 |
0 |
0 |
0 |
T5 |
64 |
0 |
0 |
0 |
T6 |
64 |
0 |
0 |
0 |
T7 |
576 |
512 |
0 |
0 |
T8 |
64 |
0 |
0 |
0 |
T9 |
64 |
0 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
64 |
0 |
0 |
T22 |
0 |
896 |
0 |
0 |
T56 |
0 |
64 |
0 |
0 |
T71 |
0 |
576 |
0 |
0 |
T72 |
0 |
768 |
0 |
0 |
T73 |
0 |
4032 |
0 |
0 |
T74 |
0 |
640 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22512 |
22009 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22512 |
22009 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22581 |
22078 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22581 |
22078 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23538 |
23035 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23538 |
23035 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23593 |
23090 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23593 |
23090 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23620 |
23117 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23620 |
23117 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23695 |
23192 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23695 |
23192 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23700 |
23197 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23700 |
23197 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22512 |
22009 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22512 |
22009 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23796 |
23293 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23796 |
23293 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23843 |
23340 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23843 |
23340 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23883 |
23380 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23883 |
23380 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22631 |
22128 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22631 |
22128 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
61 |
60 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
52 |
51 |
0 |
0 |
T8 |
102 |
101 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
11 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7158 |
6655 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7158 |
6655 |
0 |
0 |
T2 |
8 |
7 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
9 |
8 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T13 |
0 |
16 |
0 |
0 |
T21 |
541 |
540 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T23 |
0 |
26 |
0 |
0 |
T25 |
0 |
26 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9563 |
9060 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9563 |
9060 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
9 |
8 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
16 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T2,T7,T22 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9167 |
8664 |
0 |
0 |
selKnown1 |
2946 |
2443 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9167 |
8664 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
18 |
17 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
20 |
19 |
0 |
0 |
T8 |
27 |
26 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T21 |
0 |
540 |
0 |
0 |
T22 |
0 |
22 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2946 |
2443 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T2 |
11 |
10 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
9 |
8 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T71 |
0 |
9 |
0 |
0 |
T72 |
0 |
12 |
0 |
0 |
T73 |
0 |
63 |
0 |
0 |
T74 |
0 |
10 |
0 |
0 |