| | | | | | | |
gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_alert_tx[1].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon |
96.65 |
95.83 |
97.44 |
|
|
93.33 |
100.00 |
u_rst_clean_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_out_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_root_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_por_aon[0].u_por_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_por_aon[1].u_por_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
pwrmgr_rstmgr_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
rstmgr_attrs_sva_if |
100.00 |
|
|
|
|
|
100.00 |
rstmgr_cascading_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
rstmgr_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
rstmgr_rst_en_track_sva_if |
92.86 |
|
|
|
|
|
92.86 |
rstmgr_sw_rst_sva_if |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_alert_info |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_cpu_info |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_ctrl_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_i2c0 |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_i2c1 |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_i2c2 |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_io |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_io_div2 |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_io_div4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_io_div4_shadowed |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_shadowed |
96.47 |
100.00 |
100.00 |
82.35 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
82.35 |
|
|
82.35 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_lc_usb |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_spi_device |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_spi_host0 |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_spi_host1 |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_sys |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_usb |
99.29 |
100.00 |
96.43 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_d0_usb_aon |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_aon |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_io |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_io_div2 |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_io_div4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_io_div4_shadowed |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_shadowed |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_lc_usb |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_por |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_por_io |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_por_io_div2 |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_por_io_div4 |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_por_usb |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_daon_sys_io_div4 |
100.00 |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
gen_rst_chk.u_prim_rst_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
g_scan_mux.u_scan_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_chk.u_rst_chk |
100.00 |
|
|
100.00 |
|
|
|
u_prim_mubi4_sender |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_flops.u_prim_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_scanmode_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_lc_src |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
gen_rst_pd_n[0].u_pd_rst |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_pd_n[0].u_rst_pd_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_aon_rst |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_aon_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_por_clk_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_por_rst_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_reg |
99.65 |
98.40 |
99.85 |
100.00 |
|
100.00 |
100.00 |
u_alert_info |
100.00 |
100.00 |
|
|
|
|
|
u_alert_info_attr |
33.33 |
33.33 |
|
|
|
|
|
u_alert_info_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_alert_info_ctrl_index |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_alert_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_alert_test_fatal_cnsty_fault |
100.00 |
100.00 |
|
|
|
|
|
u_alert_test_fatal_fault |
100.00 |
100.00 |
|
|
|
|
|
u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
u_chk |
100.00 |
|
|
100.00 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_cpu_info |
100.00 |
100.00 |
|
|
|
|
|
u_cpu_info_attr |
33.33 |
33.33 |
|
|
|
|
|
u_cpu_info_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cpu_info_ctrl_index |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_cpu_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_err_code_fsm_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_reg_intg_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_err_code_reset_consistency_err |
96.30 |
88.89 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
u_reg_if |
98.97 |
97.14 |
98.75 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_reset_info_hw_req |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reset_info_low_power_exit |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reset_info_por |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reset_info_sw_reset |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_reset_req |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_sw_rst_ctrl_n_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_5 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_6 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_ctrl_n_7 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_sw_rst_regwen_0 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_1 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_2 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_3 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_4 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_5 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_6 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sw_rst_regwen_7 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_sys_src |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
gen_rst_pd_n[0].u_pd_rst |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rst_pd_n[0].u_rst_pd_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
u_aon_rst |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_aon_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |