Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 54 54 100.00
Total Bits 0->1 27 27 100.00
Total Bits 1->0 27 27 100.00

Ports 5 5 100.00
Port Bits 54 54 100.00
Port Bits 0->1 27 27 100.00
Port Bits 1->0 27 27 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
oh_i[4:0] Yes Yes *T4,*T6,*T10 Yes T4,T6,T10 INPUT
oh_i[6:5] Unreachable Unreachable Unreachable INPUT
oh_i[8:7] Yes Yes T21,*T57,*T68 Yes T21,T57,T68 INPUT
oh_i[10:9] Unreachable Unreachable Unreachable INPUT
oh_i[26:11] Yes Yes *T1,T21,T60 Yes T1,T21,T60 INPUT
oh_i[27] Unreachable Unreachable Unreachable INPUT
addr_i[4:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T21,T57,T68 Yes T21,T57,T68 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%