Line Coverage for Instance : tb.dut.u_reg.u_reset_req.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_reset_req.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_reset_req.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T7 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_reset_info_por.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reset_info_por.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reset_info_low_power_exit.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T7 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reset_info_sw_reset.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_reset_info_hw_req.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_alert_regwen.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_alert_regwen.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T63,T64,T65 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T63,T65,T66 |
1 | 0 | Covered | T63,T65,T66 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T63,T64,T65 |
Line Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_alert_info_ctrl_index.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cpu_regwen.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T63,T64,T65 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T63,T64,T65 |
1 | 0 | Covered | T63,T64,T65 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T63,T64,T65 |
Line Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_en.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_cpu_info_ctrl_index.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_0.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_1.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_2.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T60,T61 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T60,T61 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T60,T61 |
1 | 0 | Covered | T1,T60,T61 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_regwen_7.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T60,T61 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T60,T61,T62 |
1 | 0 | Covered | T60,T61,T62 |
1 | 1 | Covered | T1,T2,T3 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T60,T61 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T12,T24 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T12,T24 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T12,T24 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T12,T24 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T12,T24 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T12,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T12,T24 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_sw_rst_ctrl_n_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T12 |
0 |
Covered |
T1,T2,T3 |