Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.73	100.00	75.86	91.55			87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	88.73	100.00	75.86	91.55			87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.73	100.00	75.86	91.55			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.26	92.86	79.29	89.36	75.64	82.65	97.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	86.20	98.68	92.76		70.00	94.57	75.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	93.27	99.00	80.90	93.33		93.10	100.00
rv_dm_regs_csr_assert	0.00						0.00
tl_adapter_host_sba	95.14	100.00	100.00	75.71		100.00	100.00
tlul_assert_device_mem	95.24	100.00				85.71	100.00
tlul_assert_device_regs	94.54	100.00				85.71	97.90
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	84.62	86.69	65.19		100.00	71.23	100.00
u_lc_en_sync	100.00	100.00				100.00	100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	100.00	100.00	100.00				100.00
u_prim_rst_n_mux2	100.00	100.00	100.00				100.00
u_reg_regs	94.73	93.50	93.58	93.49		93.10	100.00
u_tlul_lc_gate_rom	80.36	93.94	57.50		85.71	77.14	87.50
u_tlul_lc_gate_sba	72.24	90.15	55.00		57.14	71.43	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	412	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
109	1	1
110	1	1
115	1	1
118	1	1
141	1	1
206	1	1
207	1	1
211	1	1
294	1	1
300	1	1
302	1	1
308	1	1
309	1	1
384	1	1
412	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	29	22	75.86
Logical	29	22	75.86
Non-Logical	0	0
Event	0	0

 LINE       115
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T34,T35,T36

 LINE       118
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T31,T32
1	0	Covered	T1,T3,T12
1	1	Covered	T1,T31,T32

 LINE       207
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T17

 LINE       302
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T5

 LINE       337
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T18
1	1	Covered	T1,T2,T3

 LINE       337
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       412
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T4,T9

 LINE       428
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       428
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T18
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	94	75	79.79
Total Bits	1112	1018	91.55
Total Bits 0->1	556	509	91.55
Total Bits 1->0	556	509	91.55

Ports	94	75	79.79
Port Bits	1112	1018	91.55
Port Bits 0->1	556	509	91.55
Port Bits 1->0	556	509	91.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T11,T18,T30	Yes	T21,T11,T18	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T11,T18,T30	Yes	T21,T11,T18	INPUT
scanmode_i[0]	No	No		Yes	T5,T61,T19	INPUT
scanmode_i[2:1]	No	Yes	T5,T61,T19	No		INPUT
scanmode_i[3]	No	No		Yes	T5,T61,T19	INPUT
scan_rst_ni	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
dmactive_o	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T8,T5	OUTPUT
unavailable_i	Yes	Yes	T4,T5,T20	Yes	T4,T5,T21	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T31	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T3,T12,T31	Yes	T3,T31,T4	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T3,T31,T4	Yes	T3,T31,T4	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T31	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T3,T31,T4	Yes	T3,T12,T31	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T3,T31,T4	Yes	T3,T12,T31	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T3,T31	Yes	T1,T3,T12	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T3,T31,T4	Yes	T3,T12,T31	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T31	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T37,T44,T38	Yes	T37,T40,T62	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T31,*T32	Yes	T1,T31,T32	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T43,T37,T44	Yes	T1,T31,T32	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T1,T45,T46	Yes	T1,T32,T33	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T43,*T37,*T40	Yes	T43,T37,T40	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T7,T4,T48	Yes	T7,T4,T23	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T7,T4	Yes	T7,T4,T8	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T7,T12,T23	Yes	T2,T7,T23	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T2,T7,T32	Yes	T7,T48,T23	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T7,T32,T4	Yes	T7,T4,T48	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T7,T4,T23	Yes	T7,T4,T48	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T2,T7,T4	Yes	T7,T12,T32	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T7,T4,T9	Yes	T2,T7,T12	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T2,T7,T4	Yes	T7,T12,T32	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T7,T32,T23	Yes	T7,T48,T23	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T7,T4,T9	Yes	T7,T4,T8	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T14	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T7,T4,*T8	Yes	T7,T4,T9	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T7,T4	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T7,T4,T8	Yes	T7,T4,T8	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T4,T14	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T4,T9	Yes	T7,T4,T9	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T3,*T4,*T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T2,*T3,*T12	Yes	T2,T3,T12	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T2,T3,T12	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T2,T4,T15	Yes	T2,T4,T15	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T2,T15,T63	Yes	T2,T4,T15	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T31,T32	Yes	T1,T31,T32	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T3,T4,T14	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	26769738	26720826	0	0
DmactiveOKnown_A	26769738	26720826	0	0
FpvSecCmRegWeOnehotCheck_A	26769738	70	0	0
FpvSecCmRomTlLcGateFsm_A	26769738	0	0	0
FpvSecCmSbaTlLcGateFsm_A	26769738	0	0	0
JtagRspOTdoKnown_A	11249826	11249355	0	0
JtagRspOTdoOeKnown_A	11249826	11249355	0	0
NdmresetOKnown_A	26769738	26720826	0	0
RvDmLcEnDebugVal_A	26769738	26720826	0	0
TlMemAReadyKnown_A	26769738	26720826	0	0
TlMemDValidKnown_A	26769738	26720826	0	0
TlRegsAReadyKnown_A	26769738	26720826	0	0
TlRegsDValidKnown_A	26769738	26720826	0	0
TlSbaAValidKnown_A	26769738	26720826	0	0
TlSbaDReadyKnown_A	26769738	26720826	0	0
paramCheckNrHarts	168	168	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	70	0	0
T9	2800	0	0	0
T34	23707	20	0	0
T35	6235	10	0	0
T36	0	20	0	0
T45	1141	0	0	0
T46	1189	0	0	0
T47	1181	0	0	0
T48	2645	0	0	0
T49	1217	0	0	0
T63	256474	0	0	0
T64	0	10	0	0
T65	0	10	0	0
T66	70969	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11249826	11249355	0	0
T1	109	109	0	0
T2	162889	162889	0	0
T3	164347	164336	0	0
T4	28588	28587	0	0
T7	1601	1601	0	0
T12	138568	138568	0	0
T14	115080	115068	0	0
T31	188	188	0	0
T32	107	107	0	0
T33	109	109	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11249826	11249355	0	0
T1	109	109	0	0
T2	162889	162889	0	0
T3	164347	164336	0	0
T4	28588	28587	0	0
T7	1601	1601	0	0
T12	138568	138568	0	0
T14	115080	115068	0	0
T31	188	188	0	0
T32	107	107	0	0
T33	109	109	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26769738	26720826	0	0
T1	2253	2180	0	0
T2	576928	576878	0	0
T3	408096	407365	0	0
T4	96557	96235	0	0
T7	10481	10416	0	0
T12	130709	130700	0	0
T14	36816	35906	0	0
T31	2127	2055	0	0
T32	1057	993	0	0
T33	1372	1293	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	168	168	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0