SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 672 | 672 | 0 | 0 |
OutputsKnown_A | 107078952 | 106883304 | 0 | 0 |
gen_flops.OutputDelay_A | 53539476 | 53437242 | 0 | 1008 |
gen_no_flops.OutputDelay_A | 53539476 | 53441652 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 672 | 672 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T7 | 4 | 4 | 0 | 0 |
T12 | 4 | 4 | 0 | 0 |
T14 | 4 | 4 | 0 | 0 |
T31 | 4 | 4 | 0 | 0 |
T32 | 4 | 4 | 0 | 0 |
T33 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 107078952 | 106883304 | 0 | 0 |
T1 | 9012 | 8720 | 0 | 0 |
T2 | 2307712 | 2307512 | 0 | 0 |
T3 | 1632384 | 1629460 | 0 | 0 |
T4 | 386228 | 384940 | 0 | 0 |
T7 | 41924 | 41664 | 0 | 0 |
T12 | 522836 | 522800 | 0 | 0 |
T14 | 147264 | 143624 | 0 | 0 |
T31 | 8508 | 8220 | 0 | 0 |
T32 | 4228 | 3972 | 0 | 0 |
T33 | 5488 | 5172 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53539476 | 53437242 | 0 | 1008 |
T1 | 4506 | 4354 | 0 | 6 |
T2 | 1153856 | 1153750 | 0 | 6 |
T3 | 816192 | 814658 | 0 | 6 |
T4 | 193114 | 192440 | 0 | 6 |
T7 | 20962 | 20826 | 0 | 6 |
T12 | 261418 | 261400 | 0 | 6 |
T14 | 73632 | 71734 | 0 | 6 |
T31 | 4254 | 4104 | 0 | 6 |
T32 | 2114 | 1980 | 0 | 6 |
T33 | 2744 | 2580 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53539476 | 53441652 | 0 | 0 |
T1 | 4506 | 4360 | 0 | 0 |
T2 | 1153856 | 1153756 | 0 | 0 |
T3 | 816192 | 814730 | 0 | 0 |
T4 | 193114 | 192470 | 0 | 0 |
T7 | 20962 | 20832 | 0 | 0 |
T12 | 261418 | 261400 | 0 | 0 |
T14 | 73632 | 71812 | 0 | 0 |
T31 | 4254 | 4110 | 0 | 0 |
T32 | 2114 | 1986 | 0 | 0 |
T33 | 2744 | 2586 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 168 | 168 | 0 | 0 |
OutputsKnown_A | 26769738 | 26720826 | 0 | 0 |
gen_flops.OutputDelay_A | 26769738 | 26718621 | 0 | 504 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 168 | 168 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26718621 | 0 | 504 |
T1 | 2253 | 2177 | 0 | 3 |
T2 | 576928 | 576875 | 0 | 3 |
T3 | 408096 | 407329 | 0 | 3 |
T4 | 96557 | 96220 | 0 | 3 |
T7 | 10481 | 10413 | 0 | 3 |
T12 | 130709 | 130700 | 0 | 3 |
T14 | 36816 | 35867 | 0 | 3 |
T31 | 2127 | 2052 | 0 | 3 |
T32 | 1057 | 990 | 0 | 3 |
T33 | 1372 | 1290 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 168 | 168 | 0 | 0 |
OutputsKnown_A | 26769738 | 26720826 | 0 | 0 |
gen_flops.OutputDelay_A | 26769738 | 26718621 | 0 | 504 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 168 | 168 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26718621 | 0 | 504 |
T1 | 2253 | 2177 | 0 | 3 |
T2 | 576928 | 576875 | 0 | 3 |
T3 | 408096 | 407329 | 0 | 3 |
T4 | 96557 | 96220 | 0 | 3 |
T7 | 10481 | 10413 | 0 | 3 |
T12 | 130709 | 130700 | 0 | 3 |
T14 | 36816 | 35867 | 0 | 3 |
T31 | 2127 | 2052 | 0 | 3 |
T32 | 1057 | 990 | 0 | 3 |
T33 | 1372 | 1290 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 168 | 168 | 0 | 0 |
OutputsKnown_A | 26769738 | 26720826 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26769738 | 26720826 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 168 | 168 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 168 | 168 | 0 | 0 |
OutputsKnown_A | 26769738 | 26720826 | 0 | 0 |
gen_no_flops.OutputDelay_A | 26769738 | 26720826 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 168 | 168 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 26769738 | 26720826 | 0 | 0 |
T1 | 2253 | 2180 | 0 | 0 |
T2 | 576928 | 576878 | 0 | 0 |
T3 | 408096 | 407365 | 0 | 0 |
T4 | 96557 | 96235 | 0 | 0 |
T7 | 10481 | 10416 | 0 | 0 |
T12 | 130709 | 130700 | 0 | 0 |
T14 | 36816 | 35906 | 0 | 0 |
T31 | 2127 | 2055 | 0 | 0 |
T32 | 1057 | 993 | 0 | 0 |
T33 | 1372 | 1293 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |