e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.000s | 480.026us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.840s | 130.026us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.930s | 77.220us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 2.980s | 3.077ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.070s | 134.345us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 7.110s | 2.220ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.050s | 1.079ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.182m | 20.082ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 46.700s | 15.292ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 8.960s | 2.819ms | 1 | 2 | 50.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 2.900s | 2.154ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.370s | 741.401us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.170s | 2.001ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.860s | 174.445us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.190s | 161.614us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.760s | 40.149us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.550s | 719.105us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.080s | 186.531us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.710s | 37.526us | 0 | 2 | 0.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.820s | 69.320us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.370s | 741.401us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.800s | 19.741us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.270s | 268.219us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.530s | 902.595us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.160m | 7.948ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.230m | 16.909ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 8.630s | 4.214ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.230m | 16.909ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.530s | 902.595us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.680s | 15.085us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.750s | 50.129us | 5 | 5 | 100.00 |
| V1 | TOTAL | 156 | 161 | 96.89 | |||
| V2 | idcode | rv_dm_smoke | 2.000s | 480.026us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.330s | 747.899us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.820s | 46.351us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.810s | 178.997us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 22.350s | 6.488ms | 18 | 20 | 90.00 |
| rv_dm_delayed_resp_sba_tl_access | 23.400s | 13.213ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.028m | 50.000ms | 18 | 20 | 90.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.485m | 50.000ms | 12 | 20 | 60.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.890s | 135.603us | 1 | 2 | 50.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.310s | 597.626us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.970s | 195.281us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 3.650s | 1.709ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 35.880s | 11.150ms | 14 | 40 | 35.00 | ||
| V2 | stress_all | rv_dm_stress_all | 20.430s | 6.501ms | 14 | 50 | 28.00 |
| V2 | alert_test | rv_dm_alert_test | 0.800s | 28.617us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.640s | 866.433us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.640s | 866.433us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.230m | 16.909ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.270s | 268.219us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.530s | 902.595us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.460s | 830.625us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.230m | 16.909ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.270s | 268.219us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.530s | 902.595us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.460s | 830.625us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 201 | 276 | 72.83 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.450s | 170.622us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 18.810s | 5.094ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 30.290s | 1.805ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 382 | 512 | 74.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 24 | 85.71 |
| V2 | 18 | 16 | 10 | 55.56 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 80.36 | 94.82 | 81.77 | 89.99 | 78.21 | 84.55 | 98.52 | 34.67 |
UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 45 failures:
Test rv_dm_cmderr_busy has 1 failures.
0.rv_dm_cmderr_busy.65550448877171881951272623148067311658516440889069246118913693973610773254566
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest/run.log
UVM_ERROR @ 67260042 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 67260042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 16 failures.
0.rv_dm_stress_all.33931578454482782883594828074177136771181560967031070795984188754414913398824
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 790285739 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 790285739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.93536819700127805463202056617825942306545557875897724152991070954022506648241
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6353746 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 6353746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Test rv_dm_stress_all_with_rand_reset has 27 failures.
0.rv_dm_stress_all_with_rand_reset.30505305936313099021420901564197146598945184092144134873291870348572493323677
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7314167 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7314167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all_with_rand_reset.13659190697936287214416309592333512875817798994279520828728179880726117633830
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17603639 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 17603639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
Test rv_dm_sba_tl_access has 1 failures.
8.rv_dm_sba_tl_access.55679968926436641193083046877233879709757364838560800795807287897330015191857
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 20349539 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 20349539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 16 failures:
2.rv_dm_stress_all_with_rand_reset.109361684219874565440763809024946319750071564306848199078172910630301248999717
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7444492 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 7444492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.18479317988079941811442951164354662505180484691963325570731939015216432039065
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6772878 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 6772878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
8.rv_dm_stress_all.93001422206534301713818554303658229636896509452258089099918574102225290656974
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5021044 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 5021044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all.24617917649733507543166661209252211742309288409412635070893011225226242912317
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 27973432 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 27973432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
1.rv_dm_jtag_dmi_csr_bit_bash.29679943896954823767911912183142211892356678942980866627204385668662167748109
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 8 failures.
8.rv_dm_autoincr_sba_tl_access.86995568656982188254509285169813749893806698120064290477678770559980199683386
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_autoincr_sba_tl_access.3506030965079217653332408708877957573863478818476365276237025544370292793811
Line 407, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test rv_dm_bad_sba_tl_access has 2 failures.
11.rv_dm_bad_sba_tl_access.106761522946289769477309386948037067408364482642929396943499732767978856328129
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_bad_sba_tl_access.81037073259602225839085198348410244974386316943686970272986163353930058860211
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_tap_fsm_rand_reset has 1 failures.
31.rv_dm_tap_fsm_rand_reset.26485388998687875710677068975195190486817457106058117559327142488406852713128
Line 398, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 10 failures:
3.rv_dm_tap_fsm_rand_reset.114021884559595961546631598784322156609862441849568160279110823786595166036209
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 507608336 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 507608336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_tap_fsm_rand_reset.94344249909601414839512617916283680870880618600808811008358464845495498673060
Line 352, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 18796763012 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 18796763012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 7 failures:
5.rv_dm_stress_all.33696087237637753884580406847068600005450961079891984568414009740706149875502
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 234186972 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 234186972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all.61651346020932791696669496465984623387187697906407419832651304183520869106510
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 48349852 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 48349852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
26.rv_dm_stress_all_with_rand_reset.95316210306451359191985921420948704725337866795312425139750586401514079597398
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38610005 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 38610005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.rv_dm_stress_all_with_rand_reset.34880975069285543123283755223458128365668946620806037450613976989478083608063
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26814593 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 26814593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 6 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
1.rv_dm_jtag_dmi_debug_disabled.35050134004864531155855421753718424705081581324135212702908363315770202012889
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 32040726 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3033258163 [0xb4cbd8b3])
UVM_INFO @ 32040726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 3 failures.
16.rv_dm_stress_all.34196287306413730896050051904352418334184622719045281794232065861486241332931
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 34177131 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 933347714 [0x37a1c182])
UVM_INFO @ 34177131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all.41680177485825767686231828058758886446871267378020767075283095658760153903388
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 41971620 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3603606899 [0xd6caad73])
UVM_INFO @ 41971620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rv_dm_stress_all_with_rand_reset has 2 failures.
21.rv_dm_stress_all_with_rand_reset.57659130566400203912995885054032088886059825065753451215344520195444238975145
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 149283859 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3535000110 [0xd2b3d22e])
UVM_INFO @ 149283859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all_with_rand_reset.11373264466031882021683860468940511590886855528797230156143091602302514957433
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 108329357 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3861981047 [0xe6312777])
UVM_INFO @ 108329357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 6 failures:
10.rv_dm_tap_fsm_rand_reset.74070210925440366924782403948928964047965343997861644084518438620622290049188
Line 293, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3142363873 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3142363873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_tap_fsm_rand_reset.40768382748547722276059129119117626157228702126895042247141883395899771764160
Line 343, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10171652690 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10171652690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 5 failures:
4.rv_dm_tap_fsm_rand_reset.86367466855049655638361179422517878301069179525273977217722859685196567393809
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5457009028 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5457009028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_tap_fsm_rand_reset.1032319779964145083517646958566802334542633475397906816005790425675087999117
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 974060882 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 974060882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
3.rv_dm_stress_all_with_rand_reset.82975362853077478195709891667369870967030214591780694710677067731019180146156
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 80311823 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 80311823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all_with_rand_reset.56787296369487878591953119712844066958083205604975103511726359004730427330602
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1361579612 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 1361579612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed Error-[NOA] Null object access has 2 failures:
0.rv_dm_abstractcmd_status.24242650120567444778527065161935404261177085534150934449799787191437838952247
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
1.rv_dm_abstractcmd_status.79327505362214331701786065947393601994816236967481102796882760557754578964100
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_dv_base_reg_0/dv_base_reg_pkg.sv, 73
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed * == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (* [*] vs * [*]) has 2 failures:
Test rv_dm_stress_all has 1 failures.
17.rv_dm_stress_all.64179124456476423713721880644135239638014316308550471684135442902635891576173
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8894858 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8894858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
28.rv_dm_stress_all_with_rand_reset.55941272048301276352439094303227769134015584352374329814175646048136727730449
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 73896039 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.abstractcs.busy,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 73896039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
32.rv_dm_stress_all_with_rand_reset.38093142770226361681082952191768357664310278376274143821030946644137956757516
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 455772543 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 455772543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rv_dm_stress_all_with_rand_reset.61273002092830707884819493963310725164902926071501173895713066193546085834551
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 400762515 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 400762515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:
34.rv_dm_tap_fsm_rand_reset.59951683578150748312446640834856055686660380472523970704678383375259384482494
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 663979368 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 663979368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.rv_dm_tap_fsm_rand_reset.112704097972423991882655052920204781204177645213571085294642387248330407773951
Line 391, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 11649436963 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 11649436963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * has 1 failures:
1.rv_dm_jtag_dmi_csr_hw_reset.112984314381688779241561645280581533503664254221743204953808546433850679036637
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest/run.log
UVM_ERROR @ 131979246 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: jtag_dmi_ral.progbuf_11 reset value: 0x0
UVM_INFO @ 131979246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
2.rv_dm_tap_fsm_rand_reset.4432050024112113942974682563726105507541113740316437915346810070832529940577
Line 310, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4540654936 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4540654936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
3.rv_dm_stress_all.99347895213990969164536853081482128095508877601906055468531324529144176010247
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 818271883 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 818271883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:48) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 1 failures:
11.rv_dm_sba_tl_access.33926283573216370058675072344821785246811451600483315581190445699711503301715
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 1195723 ps: (jtag_dmi_monitor.sv:48) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1195723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 1 failures:
28.rv_dm_tap_fsm_rand_reset.18725939787089960785056440550559984863070927685583361672350538352359220507771
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 2216832946 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 2216832946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
30.rv_dm_stress_all.3859060576362348874579255176992532996430318292930213062102265097306984848556
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 13205672 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13205672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
31.rv_dm_stress_all_with_rand_reset.24003317671311902608118285172177614381122691473218693848880304173320287845796
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 147182944 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (16 [0x10] vs 10055440 [0x996f10])
UVM_INFO @ 147182944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
33.rv_dm_stress_all.84742817786927484852692290487732133245678444236580222589209262294665663456436
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 193928807 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 193928807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 1 failures:
41.rv_dm_stress_all_with_rand_reset.58139550948726197111644830016172351586015720528294797863020647882923232760962
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 85195166 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 85195166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 1 failures:
42.rv_dm_stress_all.35207683025043571160411039110671155911420589932550664892838126403500299213947
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 5890531956 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x91793100)
UVM_INFO @ 5890531956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:827) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
48.rv_dm_stress_all_with_rand_reset.89021073248496826903815738469427289796184801028853245977236579761593704973411
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1632677536 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1632677536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---