Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
77.03	90.91	61.70	87.88		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24674277	13315	0	0
late_debug_enable_rd_A	24674277	2515	0	0
late_debug_enable_regwen_rd_A	24674277	2414	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24674277	13315	0	0
T40	20800	2	0	0
T41	3308	29	0	0
T42	116324	194	0	0
T64	414798	38	0	0
T65	3380	120	0	0
T72	593093	36	0	0
T73	26317	1	0	0
T74	16747	252	0	0
T75	315009	30	0	0
T76	45754	41	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24674277	2515	0	0
T42	116324	92	0	0
T64	414798	25	0	0
T75	315009	41	0	0
T76	45754	32	0	0
T85	26742	1	0	0
T96	11595	8	0	0
T112	639334	136	0	0
T113	6571	7	0	0
T114	11037	56	0	0
T115	52232	32	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24674277	2414	0	0
T42	116324	88	0	0
T64	414798	43	0	0
T75	315009	41	0	0
T76	45754	36	0	0
T80	8227	5	0	0
T85	26742	15	0	0
T112	639334	143	0	0
T113	6571	5	0	0
T114	11037	44	0	0
T115	52232	48	0	0