Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.03	90.91	61.70	87.88		57.14	87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	77.03	90.91	61.70	87.88		57.14	87.50

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.03	90.91	61.70	87.88		57.14	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	93.86	81.46	87.61	74.36	82.33	98.42

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
dap	86.33	98.68	93.42		70.00	94.57	75.00
gen_alert_tx[0].u_prim_alert_sender	83.33			83.33
i_tlul_adapter_reg	93.27	99.00	80.90	93.33		93.10	100.00
rv_dm_regs_csr_assert	100.00						100.00
tl_adapter_host_sba	95.05	100.00	100.00	75.24		100.00	100.00
tlul_assert_device_mem	95.24	100.00				85.71	100.00
tlul_assert_device_regs	95.12	100.00				85.71	99.65
tlul_assert_host_sba	94.30	100.00				85.71	97.18
u_dm_top	80.46	84.60	64.25		85.71	67.71	100.00
u_lc_en_sync_copies	100.00	100.00					100.00
u_pm_en_sync	100.00	100.00				100.00	100.00
u_prim_clock_mux2	100.00	100.00	100.00				100.00
u_prim_flop_2sync_lc_rst_assert	100.00	100.00				100.00
u_prim_flop_2sync_lc_rst_sync	100.00	100.00				100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug	100.00	100.00				100.00	100.00
u_prim_rst_n_mux2	100.00	100.00	100.00				100.00
u_reg_regs	98.19	98.69	98.71	93.55		100.00	100.00
u_tlul_lc_gate_rom	85.44	93.70	67.86		100.00	78.12	87.50
u_tlul_lc_gate_sba	74.11	89.76	64.29		57.14	71.88	87.50

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
TOTAL		33	30	90.91
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
ALWAYS	320	11	8	72.73
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	551	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
123	1	1
128	1	1
131	1	1
154	1	1
236	1	1
237	1	1
239	4	4
278	1	1
288	1	1
289	1	1
320	1	1
321	1	1
322	1	1
325	1	1
326	1	1
327	1	1
328	0	1
			MISSING_ELSE
331	1	1
332	0	1
333	1	1
334	0	1
			MISSING_ELSE
345	1	1
432	1	1
438	1	1
440	1	1
446	1	1
447	1	1
523	1	1
551	1	1

---

Cond Coverage for Module : rv_dm

	Total	Covered	Percent
Conditions	47	29	61.70
Logical	47	29	61.70
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T32,T33,T34

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T27
1	1	Covered	T1,T27,T35

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T17,T5

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T5
1	1	Covered	T16,T17,T5

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T5
1	0	Not Covered
1	1	Not Covered

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T5
1	1	Not Covered

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Not Covered
1	0	1	1	1	Covered	T16,T17,T5
1	1	0	1	1	Not Covered
1	1	1	0	1	Not Covered
1	1	1	1	0	Not Covered
1	1	1	1	1	Not Covered

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T13,T36
1	1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T13
1	0	Covered	T4,T16,T17

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T13,T36
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	98	79	80.61
Total Bits	1188	1044	87.88
Total Bits 0->1	594	522	87.88
Total Bits 1->0	594	522	87.88

Ports	98	79	80.61
Port Bits	1188	1044	87.88
Port Bits 0->1	594	522	87.88
Port Bits 1->0	594	522	87.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	INPUT
next_dm_addr_i[31:0]	No	No		No		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T13,T36	Yes	T17,T5,T13	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T17,T13,T36	Yes	T17,T5,T13	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T17,T13,T36	Yes	T17,T5,T13	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[0]	No	No		Yes	T6,T10	INPUT
scanmode_i[2:1]	No	Yes	T6,T10	No		INPUT
scanmode_i[3]	No	No		Yes	T6,T10	INPUT
scan_rst_ni	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	INPUT
ndmreset_req_o	Yes	Yes	T16,T17,T5	Yes	T16,T17,T5	OUTPUT
dmactive_o	Yes	Yes	T31,T17,T5	Yes	T1,T2,T3	OUTPUT
debug_req_o	Yes	Yes	T5,T6,T37	Yes	T4,T5,T6	OUTPUT
unavailable_i	Yes	Yes	T16,T17,T5	Yes	T16,T17,T5	INPUT
regs_tl_d_i.d_ready	Yes	Yes	T7,T4,T31	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T27	Yes	T1,T2,T27	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T27	Yes	T1,T3,T27	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T2,T7,T35	Yes	T3,T35,T5	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T3,T35,T38	Yes	T2,T35,T5	INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T1,T3,T27	Yes	T1,T3,T27	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T2,T3,T7	Yes	T3,T35,T5	INPUT
regs_tl_d_i.a_address[31:0]	Yes	Yes	T7,T35,T5	Yes	T35,T5,T38	INPUT
regs_tl_d_i.a_source[7:0]	Yes	Yes	T27,T35,T39	Yes	T2,T3,T7	INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T1,T7,T35	Yes	T1,T2,T27	INPUT
regs_tl_d_i.a_param[2:0]	Yes	Yes	T35,T5,T38	Yes	T2,T3,T35	INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T1,T27,T35	Yes	T1,T35,T39	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T1,T3,T27	Yes	T1,T3,T27	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T1,T3,T27	Yes	T1,T3,T27	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T27,*T39	Yes	T1,T27,T35	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T40,T43,T41	Yes	T1,T3,T27	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:0]	Yes	Yes	T27,T35,T39	Yes	T1,T3,T27	OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T1,T39,T44	Yes	T1,T27,T39	OUTPUT
regs_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T40,*T43,*T41	Yes	T40,T43,T41	OUTPUT
regs_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T1,T3,T27	Yes	T1,T3,T27	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T7,T4,T31	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T37	Yes	T16,T17,T45	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T27,T7,T4	Yes	T4,T16,T17	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T7,T16,T45	Yes	T27,T16,T37	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Yes	Yes	T16,T37,T13	Yes	T7,T16,T46	INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T16,T17,T37	Yes	T27,T16,T17	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T16,T17,T45	Yes	T27,T16,T39	INPUT
mem_tl_d_i.a_address[31:0]	Yes	Yes	T16,T39,T17	Yes	T16,T17,T37	INPUT
mem_tl_d_i.a_source[7:0]	Yes	Yes	T4,T16,T39	Yes	T4,T16,T17	INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T27,T4,T16	Yes	T7,T4,T16	INPUT
mem_tl_d_i.a_param[2:0]	Yes	Yes	T27,T16,T37	Yes	T16,T39,T37	INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T4,T16,T17	Yes	T27,T4,T16	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T17,T5,T6	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T16,T17,T13	Yes	T16,T17,T13	OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,T16,*T17	Yes	T4,T16,T17	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T16,T17	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:0]	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	OUTPUT
mem_tl_d_o.d_param[2:0]	No	No		No		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T16,T17,T5	OUTPUT
mem_tl_d_o.d_opcode[2:1]	No	No		No		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T17,*T5,*T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	No	No		No		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
sba_tl_h_o.a_source[7:0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[0]	Yes	Yes	*T28,*T29,*T30	Yes	T28,T29,T30	OUTPUT
sba_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T7,T4,T31	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T5,T37,T47	Yes	T35,T5,T45	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T5,T48,T28	Yes	T35,T5,T45	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T48,T28	Yes	T27,T35,T5	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T35,T5,T28	Yes	T27,T5,T45	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T5,T28,T37	Yes	T27,T35,T5	INPUT
sba_tl_h_i.d_source[7:0]	Yes	Yes	T5,T37,T33	Yes	T5,T37,T33	INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T5,T37,T47	Yes	T35,T5,T33	INPUT
sba_tl_h_i.d_param[2:0]	Yes	Yes	T35,T5,T45	Yes	T5,T37,T47	INPUT
sba_tl_h_i.d_opcode[2:0]	Yes	Yes	T35,T5,T48	Yes	T27,T5,T28	INPUT
sba_tl_h_i.d_valid	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T27,T35	Yes	T1,T27,T35	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T27,T35	Yes	T1,T27,T35	OUTPUT
jtag_i.tdi	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.trst_n	Yes	Yes	T17,T5,T6	Yes	T1,T2,T3	INPUT
jtag_i.tms	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_i.tck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
jtag_o.tdo_oe	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
jtag_o.tdo	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_dm

	Line No.	Total	Covered	Percent
Branches		7	4	57.14
IF	320	7	4	57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	if ((!rst_ni))
-2-:	325	if ((ndmreset_req && (!ndmreset_pending_q)))
-3-:	327	if ((ndmreset_ack && ndmreset_pending_q))
-4-:	331	if ((ndmreset_pending_q && lc_rst_asserted))
-5-:	333	if ((ndmreset_ack && lc_rst_pending_q))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T16,T17,T5
0	0	1	-	-	Not Covered
0	0	0	-	-	Covered	T1,T2,T3
0	-	-	1	-	Not Covered
0	-	-	0	1	Not Covered
0	-	-	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_dm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugReqOKnown_A	2070422	2053742	0	0
DmactiveOKnown_A	2070422	2053742	0	0
FpvSecCmRegWeOnehotCheck_A	2070422	90	0	0
FpvSecCmRomTlLcGateFsm_A	2070422	0	0	0
FpvSecCmSbaTlLcGateFsm_A	2070422	0	0	0
JtagRspOTdoKnown_A	1177317	1177255	0	0
JtagRspOTdoOeKnown_A	1177317	1177255	0	0
NdmresetOKnown_A	2070422	2053742	0	0
RvDmLcEnDebugVal_A	2070422	2053742	0	0
TlMemAReadyKnown_A	2070422	2053742	0	0
TlMemDValidKnown_A	2070422	2053742	0	0
TlRegsAReadyKnown_A	2070422	2053742	0	0
TlRegsDValidKnown_A	2070422	2053742	0	0
TlSbaAValidKnown_A	2070422	2053742	0	0
TlSbaDReadyKnown_A	2070422	2053742	0	0
paramCheckNrHarts	103	103	0	0

DebugReqOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

DmactiveOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	90	0	0
T11	21575	0	0	0
T13	158147	0	0	0
T18	3373	0	0	0
T32	6900	20	0	0
T33	9279	20	0	0
T34	0	20	0	0
T47	1222	0	0	0
T49	0	10	0	0
T50	0	20	0	0
T51	1650	0	0	0
T52	1361	0	0	0
T53	10386	0	0	0
T54	1543	0	0	0

FpvSecCmRomTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	0	0	0

FpvSecCmSbaTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	0	0	0

JtagRspOTdoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177317	1177255	0	0
T1	160	160	0	0
T2	6953	6953	0	0
T3	234	234	0	0
T4	29955	29955	0	0
T7	1113	1113	0	0
T16	16495	16495	0	0
T27	156	156	0	0
T31	2000	2000	0	0
T35	190	190	0	0
T39	154	154	0	0

JtagRspOTdoOeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1177317	1177255	0	0
T1	160	160	0	0
T2	6953	6953	0	0
T3	234	234	0	0
T4	29955	29955	0	0
T7	1113	1113	0	0
T16	16495	16495	0	0
T27	156	156	0	0
T31	2000	2000	0	0
T35	190	190	0	0
T39	154	154	0	0

NdmresetOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

RvDmLcEnDebugVal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlMemAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlMemDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlRegsAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlRegsDValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlSbaAValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

TlSbaDReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2070422	2053742	0	0
T1	1082	992	0	0
T2	6293	6218	0	0
T3	1840	1790	0	0
T4	113781	113688	0	0
T7	8416	8362	0	0
T16	67715	67655	0	0
T27	1251	1175	0	0
T31	5621	5547	0	0
T35	1323	1252	0	0
T39	1927	1870	0	0

paramCheckNrHarts

Name	Attempts	Real Successes	Failures	Incomplete
Total	103	103	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T27	1	1	0	0
T31	1	1	0	0
T35	1	1	0	0
T39	1	1	0	0