Module Definition
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Module : prim_mubi32_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.03 90.91 61.70 87.88 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[10].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[11].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[12].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[13].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[14].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[15].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[16].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[17].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[18].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[19].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[20].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[21].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[22].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[23].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[24].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[25].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[26].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[27].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[28].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[29].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[30].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[31].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[8].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[9].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[10].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[11].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[12].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[13].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[14].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[15].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[16].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[17].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[18].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[19].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[20].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[21].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[22].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[23].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[24].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[25].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[26].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[27].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[28].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[29].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[30].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[31].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[8].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[9].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[10].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[11].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[12].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[13].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[14].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[15].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[16].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[17].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[18].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[19].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[20].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[21].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[22].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[23].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[24].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[25].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[26].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[27].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[28].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[29].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[30].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[31].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[8].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[9].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[10].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[11].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[12].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[13].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[14].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[15].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[16].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[17].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[18].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[19].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[20].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[21].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[22].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[23].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[24].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[25].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[26].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[27].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[28].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[29].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[30].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[31].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[8].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[9].u_prim_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi32_sync
Line No.TotalCoveredPercent
TOTAL55100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 4 4


Assert Coverage for Module : prim_mubi32_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 103 103 0 0
OutputsKnown_A 2070422 2053742 0 0
gen_no_flops.OutputDelay_A 2070422 2053742 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 103 103 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T27 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0
T39 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2070422 2053742 0 0
T1 1082 992 0 0
T2 6293 6218 0 0
T3 1840 1790 0 0
T4 113781 113688 0 0
T7 8416 8362 0 0
T16 67715 67655 0 0
T27 1251 1175 0 0
T31 5621 5547 0 0
T35 1323 1252 0 0
T39 1927 1870 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2070422 2053742 0 0
T1 1082 992 0 0
T2 6293 6218 0 0
T3 1840 1790 0 0
T4 113781 113688 0 0
T7 8416 8362 0 0
T16 67715 67655 0 0
T27 1251 1175 0 0
T31 5621 5547 0 0
T35 1323 1252 0 0
T39 1927 1870 0 0

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