SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
77.03 | 90.91 | 61.70 | 87.88 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 618 | 618 | 0 | 0 |
OutputsKnown_A | 12422532 | 12322452 | 0 | 0 |
gen_flops.OutputDelay_A | 6211266 | 6158958 | 0 | 927 |
gen_no_flops.OutputDelay_A | 6211266 | 6161226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 618 | 618 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T27 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
T39 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12422532 | 12322452 | 0 | 0 |
T1 | 6492 | 5952 | 0 | 0 |
T2 | 37758 | 37308 | 0 | 0 |
T3 | 11040 | 10740 | 0 | 0 |
T4 | 682686 | 682128 | 0 | 0 |
T7 | 50496 | 50172 | 0 | 0 |
T16 | 406290 | 405930 | 0 | 0 |
T27 | 7506 | 7050 | 0 | 0 |
T31 | 33726 | 33282 | 0 | 0 |
T35 | 7938 | 7512 | 0 | 0 |
T39 | 11562 | 11220 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 6211266 | 6158958 | 0 | 927 |
T1 | 3246 | 2967 | 0 | 9 |
T2 | 18879 | 18645 | 0 | 9 |
T3 | 5520 | 5361 | 0 | 9 |
T4 | 341343 | 341055 | 0 | 9 |
T7 | 25248 | 25077 | 0 | 9 |
T16 | 203145 | 202956 | 0 | 9 |
T27 | 3753 | 3516 | 0 | 9 |
T31 | 16863 | 16632 | 0 | 9 |
T35 | 3969 | 3747 | 0 | 9 |
T39 | 5781 | 5601 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 6211266 | 6161226 | 0 | 0 |
T1 | 3246 | 2976 | 0 | 0 |
T2 | 18879 | 18654 | 0 | 0 |
T3 | 5520 | 5370 | 0 | 0 |
T4 | 341343 | 341064 | 0 | 0 |
T7 | 25248 | 25086 | 0 | 0 |
T16 | 203145 | 202965 | 0 | 0 |
T27 | 3753 | 3525 | 0 | 0 |
T31 | 16863 | 16641 | 0 | 0 |
T35 | 3969 | 3756 | 0 | 0 |
T39 | 5781 | 5610 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_flops.OutputDelay_A | 2070422 | 2052986 | 0 | 309 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2052986 | 0 | 309 |
T1 | 1082 | 989 | 0 | 3 |
T2 | 6293 | 6215 | 0 | 3 |
T3 | 1840 | 1787 | 0 | 3 |
T4 | 113781 | 113685 | 0 | 3 |
T7 | 8416 | 8359 | 0 | 3 |
T16 | 67715 | 67652 | 0 | 3 |
T27 | 1251 | 1172 | 0 | 3 |
T31 | 5621 | 5544 | 0 | 3 |
T35 | 1323 | 1249 | 0 | 3 |
T39 | 1927 | 1867 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_flops.OutputDelay_A | 2070422 | 2052986 | 0 | 309 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2052986 | 0 | 309 |
T1 | 1082 | 989 | 0 | 3 |
T2 | 6293 | 6215 | 0 | 3 |
T3 | 1840 | 1787 | 0 | 3 |
T4 | 113781 | 113685 | 0 | 3 |
T7 | 8416 | 8359 | 0 | 3 |
T16 | 67715 | 67652 | 0 | 3 |
T27 | 1251 | 1172 | 0 | 3 |
T31 | 5621 | 5544 | 0 | 3 |
T35 | 1323 | 1249 | 0 | 3 |
T39 | 1927 | 1867 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2070422 | 2053742 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_flops.OutputDelay_A | 2070422 | 2052986 | 0 | 309 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2052986 | 0 | 309 |
T1 | 1082 | 989 | 0 | 3 |
T2 | 6293 | 6215 | 0 | 3 |
T3 | 1840 | 1787 | 0 | 3 |
T4 | 113781 | 113685 | 0 | 3 |
T7 | 8416 | 8359 | 0 | 3 |
T16 | 67715 | 67652 | 0 | 3 |
T27 | 1251 | 1172 | 0 | 3 |
T31 | 5621 | 5544 | 0 | 3 |
T35 | 1323 | 1249 | 0 | 3 |
T39 | 1927 | 1867 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2070422 | 2053742 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 103 | 103 | 0 | 0 |
OutputsKnown_A | 2070422 | 2053742 | 0 | 0 |
gen_no_flops.OutputDelay_A | 2070422 | 2053742 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 103 | 103 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2070422 | 2053742 | 0 | 0 |
T1 | 1082 | 992 | 0 | 0 |
T2 | 6293 | 6218 | 0 | 0 |
T3 | 1840 | 1790 | 0 | 0 |
T4 | 113781 | 113688 | 0 | 0 |
T7 | 8416 | 8362 | 0 | 0 |
T16 | 67715 | 67655 | 0 | 0 |
T27 | 1251 | 1175 | 0 | 0 |
T31 | 5621 | 5547 | 0 | 0 |
T35 | 1323 | 1252 | 0 | 0 |
T39 | 1927 | 1870 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |