0cb61fc7e7
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 2.390s | 982.246us | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.090s | 165.279us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.880s | 66.647us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 3.560s | 792.556us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.480s | 274.749us | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 3.830s | 3.250ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 6.300s | 1.927ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.093m | 19.184ms | 4 | 5 | 80.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.034m | 18.489ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 3.920s | 2.736ms | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 5.840s | 1.672ms | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.550s | 1.528ms | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.850s | 318.598us | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.760s | 75.486us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.050s | 367.648us | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.770s | 40.198us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 0.690s | 21.786us | 0 | 2 | 0.00 |
V1 | progbuf_busy | rv_dm_progbuf_busy | 1.390s | 215.776us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.810s | 88.936us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.890s | 99.617us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.550s | 1.528ms | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.820s | 46.529us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.550s | 150.038us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.780s | 1.294ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 59.060s | 1.474ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.131m | 2.322ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 12.030s | 6.052ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.131m | 2.322ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.780s | 1.294ms | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.740s | 42.664us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.720s | 18.458us | 5 | 5 | 100.00 |
V1 | TOTAL | 158 | 161 | 98.14 | |||
V2 | idcode | rv_dm_smoke | 2.390s | 982.246us | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.090s | 108.217us | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.033m | 50.000ms | 0 | 2 | 0.00 |
V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.940s | 702.952us | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 1.970s | 534.017us | 0 | 20 | 0.00 |
rv_dm_delayed_resp_sba_tl_access | 2.220s | 610.731us | 1 | 20 | 5.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 8.570s | 11.086ms | 3 | 20 | 15.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.129m | 50.000ms | 0 | 20 | 0.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.510s | 233.026us | 1 | 2 | 50.00 |
V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
V2 | ndmreset_req | rv_dm_ndmreset_req | 2.800s | 1.382ms | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 0.840s | 99.841us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 4.090s | 1.031ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 50.460s | 17.525ms | 13 | 40 | 32.50 | ||
V2 | stress_all | rv_dm_stress_all | 13.100s | 4.069ms | 7 | 50 | 14.00 |
V2 | alert_test | rv_dm_alert_test | 0.810s | 27.733us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.800s | 233.998us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.800s | 233.998us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.131m | 2.322ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.550s | 150.038us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.780s | 1.294ms | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.380s | 901.153us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.131m | 2.322ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.550s | 150.038us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.780s | 1.294ms | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.380s | 901.153us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 127 | 276 | 46.01 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 2.070s | 368.584us | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 23.750s | 1.237ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 21.120s | 2.512ms | 0 | 50 | 0.00 |
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 310 | 512 | 60.55 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 28 | 28 | 26 | 92.86 |
V2 | 18 | 16 | 8 | 44.44 |
V2S | 10 | 2 | 2 | 20.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
79.37 | 93.86 | 81.46 | 87.61 | 74.36 | 82.33 | 98.42 | 37.55 |
UVM_ERROR (rv_dm_scoreboard.sv:250) [scoreboard] Check failed sba_item.rdata[*] == data (* [*] vs * [*])
has 41 failures:
0.rv_dm_sba_tl_access.12336851265568084790762138320123894572622053277675734326042059198749845151540
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 33630093 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 148235256 [0x8d5e3f8])
SBA item:
item: (sba_access_item@5753) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h7bf9e9a4 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5697) { a_addr: 'h7bf9e9a4 a_data: 'h8051 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24284 d_param: 'h0 d_source: 'h0 d_data: 'h8d5e3f8 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd0b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_sba_tl_access.46710041342074158107913638332258868756844880744991214043851198076860780486267
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 180657897 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 20942 [0x51ce])
SBA item:
item: (sba_access_item@5993) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'hd4946c4e wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5937) { a_addr: 'hd4946c4c a_data: 'h56bd0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h26aa3 d_param: 'h0 d_source: 'h0 d_data: 'h51ce307c d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd00 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 15 more failures.
0.rv_dm_delayed_resp_sba_tl_access.42158927063404890443853908612383060800381684525621502968382728318203330116261
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 26610094 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 218873163 [0xd0bbd4b])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'hd0bbd4b d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd43 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_delayed_resp_sba_tl_access.75529846215134445722732358828592583333557667941131868368859138076601773795920
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 87614653 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1671810717 [0x63a5ce9d])
SBA item:
item: (sba_access_item@6617) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h7f09ce1c wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6565) { a_addr: 'h7f09ce1c a_data: 'hd8abc64 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h240a5 d_param: 'h0 d_source: 'h0 d_data: 'h63a5ce9d d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd26 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 12 more failures.
0.rv_dm_bad_sba_tl_access.91534220803424345175769761400635769353175465801255476179344162161221810764419
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 429363205 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 3851646375 [0xe59375a7])
SBA item:
item: (sba_access_item@8413) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h2f50c958 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@8357) { a_addr: 'h2f50c958 a_data: 'h3730220a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h260f4 d_param: 'h0 d_source: 'h0 d_data: 'he59375a7 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd5a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
2.rv_dm_bad_sba_tl_access.91198809041560751210830763565085476799633481198136384610036950822657417076150
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 201971859 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 43777 [0xab01])
SBA item:
item: (sba_access_item@5933) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'h7f6d14e2 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5877) { a_addr: 'h7f6d14e0 a_data: 'h2f660000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h25bad d_param: 'h0 d_source: 'h0 d_data: 'hab011879 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd44 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 4 more failures.
4.rv_dm_autoincr_sba_tl_access.89278305450017665430460690577968450909469137594943512394805482634635148830927
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 29482118 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 3063129876 [0xb693a714])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'hc64311a8 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'hc64311a8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2672a d_param: 'h0 d_source: 'h0 d_data: 'hb693a714 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h1 d_user: 'heb1 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
8.rv_dm_autoincr_sba_tl_access.18990489486080212806710213988828034581018962649218179917907925147322729401947
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 312482042 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 51807 [0xca5f])
SBA item:
item: (sba_access_item@7109) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'hb58f0f96 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrBadAddr timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7071) { a_addr: 'hb58f0f94 a_data: 'h43fe0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27a81 d_param: 'h0 d_source: 'h0 d_data: 'hca5fd9e6 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'he8d a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 2 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
has 38 failures:
2.rv_dm_stress_all.41483226898111147822784067633169039081259754521696021821301976443449974284535
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2432436 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 2432436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all.94768037384124299301521084876242342656726615811210291529757663081937174366372
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1245423691 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 1245423691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
5.rv_dm_stress_all_with_rand_reset.101487803641175537762663963403189553938007410948982469147096381162287010762201
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7971837 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7971837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.10772878785183460119099601014330969142389279634776832538036288892784544752318
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18513851 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 18513851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:91) m_jtag_dmi_monitor [m_jtag_dmi_monitor] JTAG operation * != DmiOpNone in quiet period
has 14 failures:
Test rv_dm_halt_resume_whereto has 2 failures.
0.rv_dm_halt_resume_whereto.84537914013634947206836622477743345063529784561469081899105818563424796172395
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 21786195 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 21786195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_halt_resume_whereto.55154928813251820877516120068919351368497711657653800347593121798179353777232
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 20401504 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 20401504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 8 failures.
1.rv_dm_stress_all.2245707166075630336948652279903006519679572152491003971728564336319428679873
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5358052424 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 5358052424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all.74265782471399381702602688354990589689415965150192111640777114761007916173686
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14659100 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 14659100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test rv_dm_stress_all_with_rand_reset has 4 failures.
1.rv_dm_stress_all_with_rand_reset.8843694787096872111284164577613347218128147932776664981970568105911465399077
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 216249728 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 216249728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.56729567411490719393943753852129756787192328733457049613341832274426793370849
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 960286549 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 960286549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol
has 13 failures:
2.rv_dm_stress_all_with_rand_reset.53644344513050182651517956015474773019359615123522271756581070570350736414465
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11360990 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 11360990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.86340596236837581118753790150949111753157319275476538906485128368915370217747
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14751943 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 14751943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
4.rv_dm_stress_all.20593067663047586160757161279399956555398902976278666103165799974631836626425
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3417489 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 3417489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all.81111727181787736993314184956911463058990917405539147952262824924673549446726
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 101233575 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 101233575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==
gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 11 failures:
1.rv_dm_bad_sba_tl_access.62526803624902727876691546553154353891428469903791670971780329536814461834315
Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 78097247 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 78097247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_bad_sba_tl_access.19409823324489761986428204464091587492896921233105400974535697624530756336590
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 133685424 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 133685424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
5.rv_dm_autoincr_sba_tl_access.77222784169463405329861064780260321322223587071360135877467357073979983305383
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 34121268 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 34121268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_autoincr_sba_tl_access.35204588745765593449460708290126484946852040419095328884298226495447233216205
Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 157505524 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 157505524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
8.rv_dm_delayed_resp_sba_tl_access.681905418448450304166636386173964230063629743116355037787932005342362880679
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 63256763 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (3 [0x3] vs 0 [0x0])
UVM_INFO @ 63256763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*])
has 10 failures:
0.rv_dm_tap_fsm_rand_reset.78156717087826663375716367710317245958579230616760909402582033304825718539881
Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4778440856 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4778440856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_tap_fsm_rand_reset.62522919123254559331952289116159166389946413943766498716191493465622760538330
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2050491050 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2050491050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*])
has 9 failures:
0.rv_dm_stress_all.23549353219400078008074168422204635110029848655907222861007309537070101588981
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 89562686 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 89562686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_dm_stress_all.84034340931148062977015554590401564183989694993746800667939284502427712056222
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6905533 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (4294964223 [0xfffff3ff] vs 4209 [0x1071])
UVM_INFO @ 6905533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
13.rv_dm_stress_all_with_rand_reset.30288718140737397937942713063290381034165227930520407294904687520492474517995
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7595307 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (0 [0x0] vs 4209 [0x1071])
UVM_INFO @ 7595307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_dm_stress_all_with_rand_reset.83957880293910997391413012917703651875707821269726195545140001886624732629868
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5365431 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (1073742449 [0x40000271] vs 4209 [0x1071])
UVM_INFO @ 5365431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*])
has 9 failures:
2.rv_dm_tap_fsm_rand_reset.31517598646520458563722702621906675908350614453869248156045154394894095214674
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1650148309 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1650148309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_tap_fsm_rand_reset.69314513185322298391137932771922422319887597963867475674864369443654374840728
Line 382, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10437359481 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10437359481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:260) [scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (* [*] vs * [*])
has 7 failures:
Test rv_dm_autoincr_sba_tl_access has 3 failures.
1.rv_dm_autoincr_sba_tl_access.100259095026856014764220860037951173798163249114634932618969572324392746737966
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 27160023 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@6201) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h2e5967c8 wdata: { [0]: 'h2dbce8be } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6145) { a_addr: 'h2e5967c8 a_data: 'h2dbce8be a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h26a06 d_param: 'h0 d_source: 'h0 d_data: 'h5e0eb380 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cfa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
3.rv_dm_autoincr_sba_tl_access.103783864634898576953846604247372946796191152021971368243160303671790943965853
Line 296, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 89357750 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@7863) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h6eb98fe4 wdata: { [0]: 'h3298cd7d } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrOther timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7803) { a_addr: 'h6eb98fe4 a_data: 'h3298cd7d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h2450f d_param: 'h0 d_source: 'h0 d_data: 'h8589e596 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h3ebe a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 1 more failures.
Test rv_dm_sba_tl_access has 2 failures.
11.rv_dm_sba_tl_access.43565609930821461129952149739312224780798231454962759030966850675926855527697
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 45625457 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@6337) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hdeda2dc6 wdata: { [0]: 'hdd2245ef } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6181) { a_addr: 'hdeda2dc4 a_data: 'h341c0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27baf d_param: 'h0 d_source: 'h0 d_data: 'hbf2917f4 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd3c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
14.rv_dm_sba_tl_access.14248557600687517285424672379818141898208643628131855732137326920648374347782
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 27540233 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@5753) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hd797e3dc wdata: { [0]: 'h4c7814e3 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5697) { a_addr: 'hd797e3dc a_data: 'h4c7814e3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h27945 d_param: 'h0 d_source: 'h0 d_data: 'h8f9e74e2 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1c9c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_bad_sba_tl_access has 1 failures.
12.rv_dm_bad_sba_tl_access.76942309852594947569691461149764662068785700778721695434866742733843794141703
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 28911099 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@5821) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hee0e2a53 wdata: { [0]: 'h97a822c2 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5665) { a_addr: 'hee0e2a50 a_data: 'h86000000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h25448 d_param: 'h0 d_source: 'h0 d_data: 'h527a35a d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd02 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
16.rv_dm_delayed_resp_sba_tl_access.8191747753400416608862629875252233806124047020506737020744344339032425619155
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 72210065 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@7437) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h35e4ab10 wdata: { [0]: 'h83495b7d } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7281) { a_addr: 'h35e4ab10 a_data: 'h89a0a336 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27c7b d_param: 'h0 d_source: 'h0 d_data: 'h726c82f5 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd1f a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 5 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.1076971092960119310808169439037220943092866579245077135523225824161818375840
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_jtag_dtm_idle_hint has 2 failures.
0.rv_dm_jtag_dtm_idle_hint.31483076846551748459163411491111212899924095006967977239273110788368834691528
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dtm_idle_hint.110378620910911708799085420806101068179310080381402653179713007185113319011297
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
2.rv_dm_autoincr_sba_tl_access.52220000304366458744959469401358487483638788172392380299942770244163420900005
Line 314, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_tap_fsm_rand_reset has 1 failures.
39.rv_dm_tap_fsm_rand_reset.79484909730474677729834243843670160710888437656467419233863465546297001491493
Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*)
has 5 failures:
1.rv_dm_tap_fsm_rand_reset.100015410960734848792761619018751427490221938925042950465578909968642859473592
Line 325, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 9402358865 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 9402358865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_tap_fsm_rand_reset.106473710807328433442324171705284195981486218532278718867161785089043064696530
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 5581882564 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 5581882564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
46.rv_dm_stress_all_with_rand_reset.86733730555051867200287491190913444051895749449487441659018665378441260637613
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2460472826 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 2460472826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:282) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (* [*] vs * [*])
has 5 failures:
7.rv_dm_bad_sba_tl_access.66173451169302073545090146347916181989390137122671476837874520789893282216952
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 89326450 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 89326450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_bad_sba_tl_access.39729902861737805043499965218689547556095025604900771121989479674321252327412
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 15538261 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 15538261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
15.rv_dm_autoincr_sba_tl_access.57012118734142385228578024759394586753808846772717022273332589351335260192052
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 103102514 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 103102514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_autoincr_sba_tl_access.67847845832278879575579640579661792370593421135652277719096914704065414818826
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 91585928 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 91585928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:280) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (* [*] vs * [*])
has 4 failures:
0.rv_dm_autoincr_sba_tl_access.2642112742116262001712128634780588671386690083336276509278436525800950907943
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 75571905 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 75571905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_autoincr_sba_tl_access.45517354573680113722557028471321733304709994940740582641434978442170867100478
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 10924324 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 10924324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
14.rv_dm_bad_sba_tl_access.83301566938060313306118490345908064302215522159317956352417068180874893970443
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 35941424 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 35941424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
has 4 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
1.rv_dm_jtag_dmi_debug_disabled.38069859256051796164867028903342436242658958683119967588723734077790023127100
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 12246414 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 559220514 [0x21550722])
UVM_INFO @ 12246414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 3 failures.
7.rv_dm_stress_all.13506404693182833426868290547115877918133540622452588443191486082352727397652
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 16625086648 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3410214556 [0xcb43be9c])
UVM_INFO @ 16625086648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all.95527375583041102007628048436433698859998127343037721262038208819194955118607
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2920851597 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 1285975045 [0x4ca66c05])
UVM_INFO @ 2920851597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:275) [scoreboard] Check failed byte_mask == sba_tl_item.a_mask (* [*] vs * [*])
has 3 failures:
Test rv_dm_autoincr_sba_tl_access has 2 failures.
7.rv_dm_autoincr_sba_tl_access.17897821437530810784248826293867319038030200251939020815894029177400200347248
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 28967048 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (4 [0x4] vs 12 [0xc])
SBA item:
item: (sba_access_item@6225) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h440e7ef6 wdata: { [0]: 'hef312b6b } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6169) { a_addr: 'h440e7ef4 a_data: 'h2b6b0000 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h27e91 d_param: 'h0 d_source: 'h0 d_data: 'h9fafd26a d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cbd a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
10.rv_dm_autoincr_sba_tl_access.102090955023885574755472654705401184281525233671559274063106927539244785204485
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 467645650 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@20319) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hb0bec718 wdata: { [0]: 'hadf12d2e } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@20281) { a_addr: 'hb0bec718 a_data: 'hadf12d2e a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h2430e d_param: 'h0 d_source: 'h0 d_data: 'h998635c6 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cdf a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_sba_tl_access has 1 failures.
16.rv_dm_sba_tl_access.109820136991824301086148475383616108411971557738545351703870737580168493068526
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 17417821 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@5753) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hd4bf8ba4 wdata: { [0]: 'he4a9d58 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5697) { a_addr: 'hd4bf8ba4 a_data: 'he4a9d58 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h26ff6 d_param: 'h0 d_source: 'h0 d_data: 'h724d7700 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1c9f a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_*
has 2 failures:
0.rv_dm_stress_all_with_rand_reset.104643465694305774251785796909409175975856934803832951234801831151687882461856
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 318165558 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 3540334885 [0xd3053925]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 318165558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.107787565372967189162296171215677743925364376551523590173797358233656069580281
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 739898216 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 779368898 [0x2e7439c2]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 739898216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 2 failures:
8.rv_dm_tap_fsm_rand_reset.27780606726003853716829637697025512584995553971050777289598039152866237954084
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 406118131 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 406118131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_tap_fsm_rand_reset.51569798578217138430250451550421419565507661782494667671892351374468308781406
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5704317346 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5704317346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:67) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * }
has 2 failures:
15.rv_dm_stress_all.107243584652353086823049470394172977344401508664368839513615248610385302096191
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2130141 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2130141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rv_dm_stress_all.6053884731119989236722488797057423495803976470856812405313107908131450135617
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14561805 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 14561805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*])
has 2 failures:
Test rv_dm_stress_all has 1 failures.
19.rv_dm_stress_all.100883924100038332261331478957292243887452220311244616777260499668515727412365
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2293928676 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 2293928676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
49.rv_dm_stress_all_with_rand_reset.66042446664201918024906192999835549636158180969162487833502068387616162145682
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 281981964 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 281981964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.abstractdata_*
has 2 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
25.rv_dm_stress_all_with_rand_reset.101155278405063030371179938570053293966179746048126867988249668028027456683543
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32061524 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
UVM_INFO @ 32061524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
40.rv_dm_stress_all.102527532273742219893198718092580081782080421601726298244239875548947271441300
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 15009479623 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
UVM_INFO @ 15009479623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6521) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
3.rv_dm_delayed_resp_sba_tl_access.81731074600558804661843291461246934579022192209045617980000459236511424099639
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 67550424 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6521) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hdd696a75 wdata: { [0]: 'hf9605de0 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 67550424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*)
has 1 failures:
4.rv_dm_stress_all_with_rand_reset.67156858413882383242750769338907786498811513866059815917584644388440052732138
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3824172833 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x6d49e100)
UVM_INFO @ 3824172833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:142) [m_sba_access_monitor] Check failed sbbusyerror ==
gmv(jtag_dmi_ral.sbcs.sbbusyerror) (* [] vs * [])` has 1 failures:
7.rv_dm_delayed_resp_sba_tl_access.79884716961538005337714402850417981752245040618097312797214669552745722534372
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 96225808 ps: (sba_access_monitor.sv:142) [uvm_test_top.env.m_sba_access_monitor] Check failed sbbusyerror == `gmv(jtag_dmi_ral.sbcs.sbbusyerror) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 96225808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:273) [scoreboard] Check failed data == act_data (* [*] vs * [*])
has 1 failures:
9.rv_dm_autoincr_sba_tl_access.22948297928360328485755077574052733749258725040566238693660804764672894079297
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 107503543 ps: (rv_dm_scoreboard.sv:273) [uvm_test_top.env.scoreboard] Check failed data == act_data (161 [0xa1] vs 0 [0x0])
SBA item:
item: (sba_access_item@5857) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h6a3adc4 wdata: { [0]: 'hd3e62a1 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5801) { a_addr: 'h6a3adc4 a_data: 'h3e62a100 a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h2709d d_param: 'h0 d_source: 'h0 d_data: 'h87dce67c d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cbc a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 1 failures:
12.rv_dm_stress_all.49557734254760671322152140438568987564933135706112956606125980535069965615429
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5726916 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5726916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 1 failures:
15.rv_dm_stress_all_with_rand_reset.11544722161164742087363552681237920823520402750412145825648581350742216721492
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 102951189 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 102951189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5717) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
18.rv_dm_delayed_resp_sba_tl_access.49094538578199339549978330768892946836081011792068440964481181941232421293032
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 25814534 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5717) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'he248d6cd wdata: { [0]: 'h75b30210 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 25814534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*])
has 1 failures:
23.rv_dm_stress_all_with_rand_reset.31804660140243184878158759797548570815596091279564325741602361271913151261655
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45435155 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45435155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 1 failures:
28.rv_dm_tap_fsm_rand_reset.76929593868411667147371754275607746588422430456246988279754318597938109494902
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3364337583 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3364337583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 1 failures:
30.rv_dm_stress_all.44052872621115297665869586659380718604188925873380674660357277893326583692503
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 12244109586 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 12244109586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 1 failures:
30.rv_dm_stress_all_with_rand_reset.88155432343191195190203852309388921080656153739501694664872633306035978241342
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12797961 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12797961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable
has 1 failures:
32.rv_dm_stress_all_with_rand_reset.88480689276554163390411253875114965695642873276867010210635012364614091534491
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 67276003 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 67276003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen
has 1 failures:
33.rv_dm_stress_all_with_rand_reset.32466257407391843094682490443951115483212067566999562617307211950126318806079
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 692722689 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 692722689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*])
has 1 failures:
43.rv_dm_stress_all_with_rand_reset.106452754615632530699945438754259431712077260866501609826544483420681875649454
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36409638 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36409638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---