RV_DM Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.390s 982.246us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.090s 165.279us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.880s 66.647us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 3.560s 792.556us 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.480s 274.749us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.830s 3.250ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.300s 1.927ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.093m 19.184ms 4 5 80.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.034m 18.489ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.920s 2.736ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 5.840s 1.672ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.550s 1.528ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.850s 318.598us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.760s 75.486us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.050s 367.648us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.770s 40.198us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.690s 21.786us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.390s 215.776us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.810s 88.936us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.890s 99.617us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.550s 1.528ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.820s 46.529us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.550s 150.038us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.780s 1.294ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 59.060s 1.474ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.131m 2.322ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 12.030s 6.052ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.131m 2.322ms 5 5 100.00
rv_dm_csr_rw 2.780s 1.294ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.740s 42.664us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.720s 18.458us 5 5 100.00
V1 TOTAL 158 161 98.14
V2 idcode rv_dm_smoke 2.390s 982.246us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.090s 108.217us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.033m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.940s 702.952us 2 2 100.00
V2 sba rv_dm_sba_tl_access 1.970s 534.017us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 2.220s 610.731us 1 20 5.00
V2 bad_sba rv_dm_bad_sba_tl_access 8.570s 11.086ms 3 20 15.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.129m 50.000ms 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.510s 233.026us 1 2 50.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 2.800s 1.382ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.840s 99.841us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 4.090s 1.031ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 50.460s 17.525ms 13 40 32.50
V2 stress_all rv_dm_stress_all 13.100s 4.069ms 7 50 14.00
V2 alert_test rv_dm_alert_test 0.810s 27.733us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.800s 233.998us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.800s 233.998us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.131m 2.322ms 5 5 100.00
rv_dm_csr_hw_reset 2.550s 150.038us 5 5 100.00
rv_dm_csr_rw 2.780s 1.294ms 20 20 100.00
rv_dm_same_csr_outstanding 8.380s 901.153us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.131m 2.322ms 5 5 100.00
rv_dm_csr_hw_reset 2.550s 150.038us 5 5 100.00
rv_dm_csr_rw 2.780s 1.294ms 20 20 100.00
rv_dm_same_csr_outstanding 8.380s 901.153us 20 20 100.00
V2 TOTAL 127 276 46.01
V2S tl_intg_err rv_dm_sec_cm 2.070s 368.584us 5 5 100.00
rv_dm_tl_intg_err 23.750s 1.237ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 21.120s 2.512ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 310 512 60.55

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.37 93.86 81.46 87.61 74.36 82.33 98.42 37.55

Failure Buckets

Past Results