Module Definition
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Module Instance : tb.dut.u_tlul_lc_gate_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
47.72 72.55 33.33 28.57 54.17 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.17 84.25 39.29 28.57 56.25 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d 100.00 100.00
u_err_en_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_tlul_err_resp 71.59 86.36 50.00 50.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.72 96.08 77.78 71.43 83.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.72 93.70 67.86 71.43 78.12 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d 100.00 100.00
u_err_en_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_tlul_err_resp 71.59 86.36 50.00 50.00 100.00

Line Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
TOTAL514996.08
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282692.86
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 0 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Module : tlul_lc_gate
TotalCoveredPercent
Conditions181477.78
Logical181477.78
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T9,T6
11CoveredT5,T9,T6

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT5,T9,T17
10CoveredT1,T2,T3
11CoveredT5,T9,T6

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T6

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T6

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T9,T6

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT5,T10,T11

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Module : tlul_lc_gate
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 5 71.43
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Covered T5,T10,T11
StOutstanding 174 Covered T5,T10,T11


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T5,T10,T11
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Covered T5,T10,T11
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Not Covered
StOutstanding->StFlush 184 Covered T5,T10,T11



Branch Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
Branches 24 20 83.33
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 10 71.43
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T9,T6
0 0 1 Covered T5,T9,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T5,T10,T11
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Covered T5,T9,T6
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Covered T5,T10,T11
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T5,T10,T11
StFlush - - - 0 0 - - Covered T5,T10,T11
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_lc_gate
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 5278168 0 0 0
u_state_regs_A 5278168 5251146 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5278168 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5278168 5251146 0 0
T1 2594 2480 0 0
T2 2286 2156 0 0
T3 1902 1800 0 0
T4 5186 5038 0 0
T5 312698 311892 0 0
T21 4660 4520 0 0
T22 2948 2808 0 0
T23 4310 4148 0 0
T24 17504 14678 0 0
T25 2684 2578 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Line No.TotalCoveredPercent
TOTAL513772.55
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS1536466.67
ALWAYS164281657.14
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 0 1
157 1 1
158 0 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 0 1
MISSING_ELSE
176 1 1
177 0 1
MISSING_ELSE
182 0 1
183 0 1
184 0 1
186 0 1
191 0 1
192 0 1
193 0 1
194 0 1
195 0 1
196 0 1
==> MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
TotalCoveredPercent
Conditions18633.33
Logical18633.33
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Summary for FSM :: state_q
TotalCoveredPercent
States 5 3 60.00 (Not included in score)
Transitions 7 2 28.57
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Not Covered
StOutstanding 174 Not Covered


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Not Covered
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Not Covered
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Not Covered
StOutstanding->StFlush 184 Not Covered



Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Line No.TotalCoveredPercent
Branches 24 13 54.17
IF 144 2 2 100.00
IF 153 4 2 50.00
CASE 171 14 5 35.71
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Not Covered
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Not Covered
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Not Covered
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Not Covered
StFlush - - - 0 0 - - Not Covered
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 2639084 0 0 0
u_state_regs_A 2639084 2625573 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Line No.TotalCoveredPercent
TOTAL514996.08
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282692.86
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 0 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
TotalCoveredPercent
Conditions181477.78
Logical181477.78
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T9,T6
11CoveredT5,T9,T6

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT5,T9,T17
10CoveredT1,T2,T3
11CoveredT5,T9,T6

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T6

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T9,T6

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T9,T6

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT5,T10,T11

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 5 71.43
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Covered T5,T10,T11
StOutstanding 174 Covered T5,T10,T11


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T5,T10,T11
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Covered T5,T10,T11
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Not Covered
StOutstanding->StFlush 184 Covered T5,T10,T11



Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Line No.TotalCoveredPercent
Branches 24 20 83.33
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 10 71.43
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T9,T6
0 0 1 Covered T5,T9,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T5,T10,T11
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Covered T5,T9,T6
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Covered T5,T10,T11
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T5,T10,T11
StFlush - - - 0 0 - - Covered T5,T10,T11
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 2639084 0 0 0
u_state_regs_A 2639084 2625573 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%