Module Definition
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Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
47.72 72.55 33.33 28.57 54.17 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.72 96.08 77.78 71.43 83.33 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 438 438 0 0
OutputsKnown_A 15834504 15753438 0 0
gen_flops.OutputDelay_A 7917252 7874910 0 657
gen_no_flops.OutputDelay_A 7917252 7876719 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438 438 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T21 6 6 0 0
T22 6 6 0 0
T23 6 6 0 0
T24 6 6 0 0
T25 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 15834504 15753438 0 0
T1 7782 7440 0 0
T2 6858 6468 0 0
T3 5706 5400 0 0
T4 15558 15114 0 0
T5 938094 935676 0 0
T21 13980 13560 0 0
T22 8844 8424 0 0
T23 12930 12444 0 0
T24 52512 44034 0 0
T25 8052 7734 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7917252 7874910 0 657
T1 3891 3711 0 9
T2 3429 3225 0 9
T3 2853 2691 0 9
T4 7779 7548 0 9
T5 469047 467784 0 9
T21 6990 6771 0 9
T22 4422 4203 0 9
T23 6465 6213 0 9
T24 26256 21828 0 9
T25 4026 3858 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7917252 7876719 0 0
T1 3891 3720 0 0
T2 3429 3234 0 0
T3 2853 2700 0 0
T4 7779 7557 0 0
T5 469047 467838 0 0
T21 6990 6780 0 0
T22 4422 4212 0 0
T23 6465 6222 0 0
T24 26256 22017 0 0
T25 4026 3867 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_flops.OutputDelay_A 2639084 2624970 0 219


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2624970 0 219
T1 1297 1237 0 3
T2 1143 1075 0 3
T3 951 897 0 3
T4 2593 2516 0 3
T5 156349 155928 0 3
T21 2330 2257 0 3
T22 1474 1401 0 3
T23 2155 2071 0 3
T24 8752 7276 0 3
T25 1342 1286 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_flops.OutputDelay_A 2639084 2624970 0 219


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2624970 0 219
T1 1297 1237 0 3
T2 1143 1075 0 3
T3 951 897 0 3
T4 2593 2516 0 3
T5 156349 155928 0 3
T21 2330 2257 0 3
T22 1474 1401 0 3
T23 2155 2071 0 3
T24 8752 7276 0 3
T25 1342 1286 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_no_flops.OutputDelay_A 2639084 2625573 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_flops.OutputDelay_A 2639084 2624970 0 219


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2624970 0 219
T1 1297 1237 0 3
T2 1143 1075 0 3
T3 951 897 0 3
T4 2593 2516 0 3
T5 156349 155928 0 3
T21 2330 2257 0 3
T22 1474 1401 0 3
T23 2155 2071 0 3
T24 8752 7276 0 3
T25 1342 1286 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_no_flops.OutputDelay_A 2639084 2625573 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 73 73 0 0
OutputsKnown_A 2639084 2625573 0 0
gen_no_flops.OutputDelay_A 2639084 2625573 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 73 73 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0
T24 1 1 0 0
T25 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2639084 2625573 0 0
T1 1297 1240 0 0
T2 1143 1078 0 0
T3 951 900 0 0
T4 2593 2519 0 0
T5 156349 155946 0 0
T21 2330 2260 0 0
T22 1474 1404 0 0
T23 2155 2074 0 0
T24 8752 7339 0 0
T25 1342 1289 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%