RV_DM Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 9.090s 3.090ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 4.750s 1.592ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.190s 577.088us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.463m 58.417ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.210s 3.796ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 35.320s 12.707ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 24.730s 14.343ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.499m 100.000ms 1 5 20.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.962m 150.000ms 4 5 80.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 41.920s 15.071ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 6.810s 8.267ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.330s 577.813us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.510s 3.250ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.390s 457.752us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.440s 2.058ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.910s 88.056us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.090s 935.715us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 2.810s 2.758ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.950s 101.044us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.340s 396.349us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.330s 577.813us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.880s 82.823us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.330s 292.030us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.750s 374.601us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.103m 10.247ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.270m 4.583ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 6.210s 3.057ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.270m 4.583ms 5 5 100.00
rv_dm_csr_rw 2.750s 374.601us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.890s 81.854us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.940s 112.638us 5 5 100.00
V1 TOTAL 156 161 96.89
V2 idcode rv_dm_smoke 9.090s 3.090ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 5.020s 1.549ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.550s 516.285us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.130s 999.048us 2 2 100.00
V2 sba rv_dm_sba_tl_access 7.010m 150.000ms 19 20 95.00
rv_dm_delayed_resp_sba_tl_access 2.482m 91.619ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 6.796m 150.000ms 17 20 85.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 7.140m 150.000ms 10 20 50.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.750s 764.987us 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 3.610s 944.680us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.680s 341.030us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 17.390s 10.948ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 6.566m 150.000ms 9 40 22.50
V2 stress_all rv_dm_stress_all 1.971h 10.000s 29 50 58.00
V2 alert_test rv_dm_alert_test 1.160s 179.440us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.920s 366.914us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.920s 366.914us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.270m 4.583ms 5 5 100.00
rv_dm_csr_hw_reset 2.330s 292.030us 5 5 100.00
rv_dm_csr_rw 2.750s 374.601us 20 20 100.00
rv_dm_same_csr_outstanding 8.630s 4.439ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.270m 4.583ms 5 5 100.00
rv_dm_csr_hw_reset 2.330s 292.030us 5 5 100.00
rv_dm_csr_rw 2.750s 374.601us 20 20 100.00
rv_dm_same_csr_outstanding 8.630s 4.439ms 20 20 100.00
V2 TOTAL 210 276 76.09
V2S tl_intg_err rv_dm_sec_cm 3.580s 972.112us 5 5 100.00
rv_dm_tl_intg_err 30.300s 6.143ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.879m 8.050ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 391 512 76.37

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 11 61.11
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.41 94.66 81.18 86.65 71.79 84.50 97.89 32.17

Failure Buckets

Past Results