01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 9.090s | 3.090ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 4.750s | 1.592ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.190s | 577.088us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 1.463m | 58.417ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 4.210s | 3.796ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 35.320s | 12.707ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 24.730s | 14.343ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 4.499m | 100.000ms | 1 | 5 | 20.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.962m | 150.000ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 41.920s | 15.071ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 6.810s | 8.267ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.330s | 577.813us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.510s | 3.250ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.390s | 457.752us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.440s | 2.058ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.910s | 88.056us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.090s | 935.715us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 2.810s | 2.758ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.950s | 101.044us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.340s | 396.349us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.330s | 577.813us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.880s | 82.823us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.330s | 292.030us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.750s | 374.601us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.103m | 10.247ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.270m | 4.583ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 6.210s | 3.057ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.270m | 4.583ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.750s | 374.601us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.890s | 81.854us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.940s | 112.638us | 5 | 5 | 100.00 |
| V1 | TOTAL | 156 | 161 | 96.89 | |||
| V2 | idcode | rv_dm_smoke | 9.090s | 3.090ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 5.020s | 1.549ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.550s | 516.285us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.130s | 999.048us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 7.010m | 150.000ms | 19 | 20 | 95.00 |
| rv_dm_delayed_resp_sba_tl_access | 2.482m | 91.619ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 6.796m | 150.000ms | 17 | 20 | 85.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 7.140m | 150.000ms | 10 | 20 | 50.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.750s | 764.987us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 3.610s | 944.680us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.680s | 341.030us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 17.390s | 10.948ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 6.566m | 150.000ms | 9 | 40 | 22.50 | ||
| V2 | stress_all | rv_dm_stress_all | 1.971h | 10.000s | 29 | 50 | 58.00 |
| V2 | alert_test | rv_dm_alert_test | 1.160s | 179.440us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.920s | 366.914us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.920s | 366.914us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.270m | 4.583ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.330s | 292.030us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.750s | 374.601us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.630s | 4.439ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.270m | 4.583ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.330s | 292.030us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.750s | 374.601us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.630s | 4.439ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 210 | 276 | 76.09 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.580s | 972.112us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 30.300s | 6.143ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.879m | 8.050ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 391 | 512 | 76.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 26 | 92.86 |
| V2 | 18 | 16 | 11 | 61.11 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 78.41 | 94.66 | 81.18 | 86.65 | 71.79 | 84.50 | 97.89 | 32.17 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
0.rv_dm_tap_fsm_rand_reset.89683370084163032672697269072446313292019566796842905294076945062280019404174
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 7703635370 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7703635370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_tap_fsm_rand_reset.4148970511773417769682863007424270059752312424721071064078757015340735841455
Line 318, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 36574389568 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 36574389568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
27.rv_dm_stress_all_with_rand_reset.73533542654015949138391700048388825222453600491006926032154968869612752378271
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 591512152 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 591512152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rv_dm_stress_all_with_rand_reset.89074866543595450512880135613548113230542463412739041374203756321199676152621
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1006635845 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1006635845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 22 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 4 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.39763883318518236833287000774819187384213906675051594521015964606897478129472
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_csr_bit_bash.26724695725183846260082353689033118848042595654006971131383024242853197035864
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 100000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test rv_dm_bad_sba_tl_access has 3 failures.
0.rv_dm_bad_sba_tl_access.44297148963012319261074808250902520343515810017774876351888982644745842945983
Line 296, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_bad_sba_tl_access.64769793620400703405735945486113431112660901154807901973730968791023437043468
Line 368, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rv_dm_autoincr_sba_tl_access has 10 failures.
0.rv_dm_autoincr_sba_tl_access.64692388872376425974950203889044625536193589169596301427106791456478734729267
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.31822873106524899354192968806315514701159419865466743603361768241441934117029
Line 413, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test rv_dm_jtag_dmi_csr_aliasing has 1 failures.
1.rv_dm_jtag_dmi_csr_aliasing.4014758035033642257067764176723819252913703601821102867062113433267923430791
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_sba_tl_access has 1 failures.
2.rv_dm_sba_tl_access.46576683871054804087173030312821826881444133042501239573793649875849146716518
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more tests.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 10 failures:
0.rv_dm_stress_all_with_rand_reset.42797224475253122210800187347772652907961779903495071748025666005395070636344
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5126398516 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2457469982 [0x927a041e]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 5126398516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_stress_all_with_rand_reset.57252507536341904258051616587914805541415477233280464762047650501106940273180
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1211853548 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1479555330 [0x58303902]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 1211853548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 10 failures:
3.rv_dm_stress_all.104208216056336410227662887418711697160160576688505728074110162518628847737134
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10094353255 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 3582882393 [0xd58e7259])
UVM_INFO @ 10094353255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_stress_all.84579568912440028679347566421740815331807401110079169905614135107761093982112
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 37579708641 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 3094968948 [0xb8797a74])
UVM_INFO @ 37579708641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
6.rv_dm_stress_all_with_rand_reset.108964576452210499027647808966745935047042885276826026628856362447764175449163
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1398018570 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4219068926 [0xfb79e1fe] vs 1304688894 [0x4dc3f8fe])
UVM_INFO @ 1398018570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all_with_rand_reset.101124975325372763396052736739159423110043408386138181417428283247000771222248
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 415197296 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (484141873 [0x1cdb6b31] vs 484152533 [0x1cdb94d5])
UVM_INFO @ 415197296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:193) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 9 failures:
5.rv_dm_stress_all_with_rand_reset.39647848270865466816465920676942405171617478812642764644293216504355934952205
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1100834192 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 1100834192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_stress_all_with_rand_reset.101799546741734735491767594672324278348881536751577068044556814921634566802550
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 890761989 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 890761989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
47.rv_dm_stress_all.1048870034243514242425995885069646990099209232125119931013759642124826201216
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9231651716 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 9231651716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:193) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 7 failures:
1.rv_dm_stress_all_with_rand_reset.28571757094422357989413683670937522347367407902082517272792066964699794848023
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4348642380 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 4348642380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.89482240323715174763514607986931750037124691570388084516895252433123047329436
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3266775979 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 3266775979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 5 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
16.rv_dm_stress_all_with_rand_reset.107711543540970501419822747992090763771103630496639266272303923511556015270664
Line 299, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8050484250 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xede05100)
UVM_INFO @ 8050484250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all_with_rand_reset.107870106392553787513881107052380304763494235925083388982967946632087344245259
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 6016185610 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x61e79100)
UVM_INFO @ 6016185610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 3 failures.
17.rv_dm_stress_all.3745471073760712276131548669928567728351687397061409088327762362496409274505
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 3785834921 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x8d79d100)
UVM_INFO @ 3785834921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_stress_all.94989949598976562680815653934249008604565374758081904392670834637807119999182
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 3601523533 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x8dd8c100)
UVM_INFO @ 3601523533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:73) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 4 failures:
2.rv_dm_tap_fsm_rand_reset.91714019889367361566180667921909890710684961816758330917711156026603970943078
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 56160717584 ps: (rv_dm_smoke_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 56160717584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_tap_fsm_rand_reset.50283523968024810702256382360937051079261461870085111852145211694498586136642
Line 359, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 52294915695 ps: (rv_dm_smoke_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 52294915695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
6.rv_dm_stress_all.64610939334061175128712795422316883425400218692869074303120000027017878501056
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
Job ID: smart:8358d6f8-5122-4957-95c3-5f042eaf4db8
19.rv_dm_stress_all.96410685450807542653887757919425543190602333204510493487774919910200884017815
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log
Job ID: smart:d9baa377-52a1-4f73-b2d1-1ae376cc81d7
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 4 failures:
9.rv_dm_stress_all_with_rand_reset.44163898889707756156064742692291704859510747053106603696259338997147477731914
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 241919949 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 241919949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.87254400079981749237900036856473265751075259620662529365592390565033938950004
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2568285259 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 2568285259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 4 failures:
13.rv_dm_stress_all.59685594921016669519433890262684076332044101806760303597791906445103306228074
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 556100575 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 556100575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rv_dm_stress_all.74460758652160429519835948409079662378035762434899846574150191816511829172908
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1572360835 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 1572360835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 3 failures:
3.rv_dm_stress_all_with_rand_reset.2430479823194681261738495082828596822982881934168580223830563048758544761049
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 835544188 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (20 [0x14] vs 59918 [0xea0e])
UVM_INFO @ 835544188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.95807652430858225040149555300681060724804459095896763029581975093765084029256
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 642450722 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (8 [0x8] vs 122 [0x7a])
UVM_INFO @ 642450722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:
14.rv_dm_tap_fsm_rand_reset.69201778808571039750255180956871035864479533019388100615692858775984425183517
Line 296, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 15556413892 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 15556413892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_tap_fsm_rand_reset.67409363654472731513988747871038828880292970566227362408653813671512417524416
Line 314, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 38303012359 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 38303012359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 2 failures:
4.rv_dm_stress_all_with_rand_reset.27204670704905963319355617176456214447178174477217282481226506319399108107266
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3514301126 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3514301126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_dm_stress_all_with_rand_reset.27075317977316983239337410010835185586344880473551151519636369075174998224324
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5272218146 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5272218146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:42) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 2 failures:
7.rv_dm_stress_all_with_rand_reset.44920815129932392597687128719145167463809254834652610016842934650516543988684
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 821668083 ps: (rv_dm_halt_resume_whereto_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 2 [0x2])
UVM_INFO @ 821668083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rv_dm_stress_all_with_rand_reset.82738555210349803970744578566691304044721735422299380616585747612179744307383
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2777417059 ps: (rv_dm_halt_resume_whereto_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2777417059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 2 failures:
15.rv_dm_stress_all.1600889998451285152873076806101487817005078876787789043738972900287484109944
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 385312037 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (274877906948 [0x4000000004] vs 4209 [0x1071])
UVM_INFO @ 385312037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all.19094493562599684100291904836037247277501072677786602283888934689446800788409
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 790971157 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (274877906948 [0x4000000004] vs 4209 [0x1071])
UVM_INFO @ 790971157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:39) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 2 failures:
26.rv_dm_stress_all_with_rand_reset.81749580118701458627603003225007898718568046291053008165646640537443162571309
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3149640693 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3149640693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.rv_dm_stress_all_with_rand_reset.17263603879961742713495131999443427258156779864423561941471707236529724348931
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 411777636 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 411777636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd rv_dm_mem_reg_block.flags_* (addr=*) has 1 failures:
7.rv_dm_tap_fsm_rand_reset.87877784504225978194350228749668769853339812992383697437814082555224116427017
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 23299810068 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd rv_dm_mem_reg_block.flags_84 (addr=0xc1279550)
UVM_INFO @ 23299810068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:35) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all_with_rand_reset.93398141541466013760105669076136162028101591791537609209237938963334909144361
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 181606756 ps: (rv_dm_halt_resume_whereto_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 181606756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*]) has 1 failures:
21.rv_dm_stress_all.27437410332543142215318677289167770357911927317700421509115483848263449552855
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14665446576 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14665446576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 1 failures:
23.rv_dm_stress_all.574276771879358749564866631931515067114301441136419371496520629928312071799
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 118640191 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 118640191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---