RV_DM Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 7.760s 2.675ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.730s 714.629us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 4.210s 1.289ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 20.030s 22.537ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.790s 1.319ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 16.360s 5.750ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 28.320s 9.514ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 47.920s 53.654ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.807m 150.000ms 4 5 80.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 12.140s 10.010ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 28.970s 9.600ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.610s 1.241ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.210s 897.106us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.120s 141.887us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.900s 2.211ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.930s 198.680us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.400s 2.623ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 4.030s 4.223ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.040s 207.765us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.090s 158.035us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.610s 1.241ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.840s 100.528us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.670s 755.907us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.620s 105.774us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 51.430s 5.896ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.293m 4.022ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.400s 6.459ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.293m 4.022ms 5 5 100.00
rv_dm_csr_rw 2.620s 105.774us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.770s 71.261us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.720s 31.698us 5 5 100.00
V1 TOTAL 175 176 99.43
V2 idcode rv_dm_smoke 7.760s 2.675ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 5.640s 1.537ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.200s 244.822us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.310s 2.159ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 31.220s 12.158ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 26.730s 9.375ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 18.700s 6.307ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 3.197m 131.919ms 19 20 95.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.270s 571.586us 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 11.210s 3.907ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.340s 229.307us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 32.560s 11.159ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.118m 150.000ms 9 10 90.00
V2 stress_all rv_dm_stress_all 2.570h 10.000s 21 50 42.00
V2 alert_test rv_dm_alert_test 1.070s 140.598us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 7.100s 1.581ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 7.100s 1.581ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.293m 4.022ms 5 5 100.00
rv_dm_csr_hw_reset 2.670s 755.907us 5 5 100.00
rv_dm_csr_rw 2.620s 105.774us 20 20 100.00
rv_dm_same_csr_outstanding 8.090s 596.734us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.293m 4.022ms 5 5 100.00
rv_dm_csr_hw_reset 2.670s 755.907us 5 5 100.00
rv_dm_csr_rw 2.620s 105.774us 20 20 100.00
rv_dm_same_csr_outstanding 8.090s 596.734us 20 20 100.00
V2 TOTAL 215 246 87.40
V2S tl_intg_err rv_dm_sec_cm 4.630s 1.398ms 5 5 100.00
rv_dm_tl_intg_err 23.760s 5.634ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.148m 4.170ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 415 497 83.50

Testplan Progress

Items Total Written Passing Progress
V1 28 28 27 96.43
V2 18 16 13 72.22
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.40 94.56 78.98 86.17 70.51 84.50 98.52 42.55

Failure Buckets

Past Results