a8c9c17a8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 7.760s | 2.675ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.730s | 714.629us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 4.210s | 1.289ms | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 20.030s | 22.537ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 3.790s | 1.319ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 16.360s | 5.750ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 28.320s | 9.514ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 47.920s | 53.654ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.807m | 150.000ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 12.140s | 10.010ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 28.970s | 9.600ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.610s | 1.241ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 3.210s | 897.106us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.120s | 141.887us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.900s | 2.211ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.930s | 198.680us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 4.400s | 2.623ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 4.030s | 4.223ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.040s | 207.765us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.090s | 158.035us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.610s | 1.241ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.840s | 100.528us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.670s | 755.907us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.620s | 105.774us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 51.430s | 5.896ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.293m | 4.022ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 8.400s | 6.459ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.293m | 4.022ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.620s | 105.774us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.770s | 71.261us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.720s | 31.698us | 5 | 5 | 100.00 |
| V1 | TOTAL | 175 | 176 | 99.43 | |||
| V2 | idcode | rv_dm_smoke | 7.760s | 2.675ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 5.640s | 1.537ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.200s | 244.822us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.310s | 2.159ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 31.220s | 12.158ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 26.730s | 9.375ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 18.700s | 6.307ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 3.197m | 131.919ms | 19 | 20 | 95.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.270s | 571.586us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 11.210s | 3.907ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.340s | 229.307us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 32.560s | 11.159ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 3.118m | 150.000ms | 9 | 10 | 90.00 | ||
| V2 | stress_all | rv_dm_stress_all | 2.570h | 10.000s | 21 | 50 | 42.00 |
| V2 | alert_test | rv_dm_alert_test | 1.070s | 140.598us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 7.100s | 1.581ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 7.100s | 1.581ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.293m | 4.022ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.670s | 755.907us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.620s | 105.774us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.090s | 596.734us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.293m | 4.022ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.670s | 755.907us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.620s | 105.774us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.090s | 596.734us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 215 | 246 | 87.40 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 4.630s | 1.398ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 23.760s | 5.634ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.148m | 4.170ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 415 | 497 | 83.50 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 27 | 96.43 |
| V2 | 18 | 16 | 13 | 72.22 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 79.40 | 94.56 | 78.98 | 86.17 | 70.51 | 84.50 | 98.52 | 42.55 |
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
0.rv_dm_stress_all.103078522284459790827498451586699495516903804781171792722285550308956960909881
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
Job ID: smart:64344b1f-83d9-4b5f-b5ff-30255d8fc006
2.rv_dm_stress_all.85747524229772300633151746367956252628250281785627457734290915773709126753189
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
Job ID: smart:362a2eb5-f82d-4048-9561-94499d22a18c
... and 14 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:
Test rv_dm_jtag_dmi_csr_aliasing has 1 failures.
1.rv_dm_jtag_dmi_csr_aliasing.82156533280584900121284991202472625728550548921151526859551880203690049210948
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 6 failures.
1.rv_dm_stress_all.83625641267595560306779660093895871410699518543945864371047546670082871075200
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all.42494256670068394816427179526312120183037161810840730450242633159457107558258
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test rv_dm_tap_fsm_rand_reset has 1 failures.
3.rv_dm_tap_fsm_rand_reset.85698640139907519394866565170535164120570666478216787012237968950338060522913
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
13.rv_dm_autoincr_sba_tl_access.67510093910744837137398248538060773610732555680172516025815120952536785968677
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 8 failures:
2.rv_dm_stress_all_with_rand_reset.48366518363073915468950414819811723509016609191754028700132428829661776228590
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2792780599 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2458640720 [0x928be150]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 2792780599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.111185220384334417739975000927241999487697992528134264348061523392931625487876
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 520738717 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 2586589446 [0x9a2c3906]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 520738717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 7 failures:
9.rv_dm_stress_all_with_rand_reset.60032512595904316067780866160236509686975157607009649042714995390907694873584
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3518803606 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 3518803606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_stress_all_with_rand_reset.21533510694490254616194953939730769761631472475849275716110639667464308251946
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 288134446 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 288134446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 7 failures:
12.rv_dm_stress_all_with_rand_reset.105185404819537623155147611957687287757807824402312382768488954680802152805992
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15556132431 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 15556132431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_stress_all_with_rand_reset.96877740708279535578695113041079380947215332601177857150998479661576498535691
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 540462760 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 540462760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 6 failures:
1.rv_dm_stress_all_with_rand_reset.52987457826236450341082535025838504182949571360940177477183549982955809167499
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 382263972 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (397554924 [0x17b234ec] vs 162673900 [0x9b234ec])
UVM_INFO @ 382263972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.95234918929944426452256041897857546823059167670108907345295715955722402331519
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4169721107 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (961380161 [0x394d7f41] vs 968548506 [0x39bae09a])
UVM_INFO @ 4169721107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
40.rv_dm_stress_all.3333774147956712028790722860292253060510535717611138742302398984545460491081
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 12516213131 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 687176230 [0x28f57a26])
UVM_INFO @ 12516213131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 6 failures:
5.rv_dm_stress_all_with_rand_reset.17329127335217773702611335057861919428126212326925128875780258565414174475048
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 213216680 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 213216680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_dm_stress_all_with_rand_reset.113691582710675263560002314522680765282220892653897508445599615729293079106925
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 305429028 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 305429028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 5 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
0.rv_dm_stress_all_with_rand_reset.27806341557556988902808065336370845837789355958882178920244871234314678661473
Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4976736109 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xccb96100)
UVM_INFO @ 4976736109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rv_dm_stress_all_with_rand_reset.60417879628037276495273447188630095132246421814315697773224332207115926154651
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8247796235 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xfea0c100)
UVM_INFO @ 8247796235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 3 failures.
9.rv_dm_stress_all.27698121987206838501449995142357304295044841151299515902391726276569815349447
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 17549896288 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x5f55e100)
UVM_INFO @ 17549896288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rv_dm_stress_all.65422959555279702228323141721520447948105126629428352367275206510490136500917
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 4937751252 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xce97a100)
UVM_INFO @ 4937751252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 4 failures:
6.rv_dm_stress_all_with_rand_reset.93209483638052110290259079105818110041654836953732010705142952815592787343114
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 371351371 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (29 [0x1d] vs 0 [0x0])
UVM_INFO @ 371351371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all_with_rand_reset.14187688663159193044278553277203820943683147971070632704286747022793511440334
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1575691502 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 66 [0x42])
UVM_INFO @ 1575691502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 3 failures:
12.rv_dm_stress_all.74175192106169655412089658964092419575246185591143267996730914239801629085589
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 30200688634 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 30200688634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_dm_stress_all.37063662866248811950148988905937210343052448890096262979060767255576193668179
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7412084076 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7412084076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
13.rv_dm_stress_all_with_rand_reset.62737706163440733674995245252651659636769826677556915367889399183714867565542
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 828316894 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 828316894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all_with_rand_reset.104714220043971001386911242433720017073659999971476181941615649084733746363875
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 985873565 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 985873565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:40) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (* [*] vs * [*]) has 2 failures:
30.rv_dm_stress_all_with_rand_reset.70749464407285835163728166398171924361748956242114740783152863897617515009837
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1071717388 ps: (rv_dm_ndmreset_req_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1071717388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_dm_stress_all_with_rand_reset.74091073769531262953774978136115791627963137175628992956687846456759638556022
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66873914 ps: (rv_dm_ndmreset_req_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 66873914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
8.rv_dm_stress_all_with_rand_reset.19766401444388651047116542790048569799882139554810191325486840949248561871878
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 462460482 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 462460482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_* (addr=*) has 1 failures:
18.rv_dm_stress_all_with_rand_reset.21891355932662186248390581057220755946094357357388768163441972429400143940828
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3308497138 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_0 (addr=0x462cb380)
UVM_INFO @ 3308497138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:51) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
25.rv_dm_stress_all_with_rand_reset.59469583018611210269719567558385613672220084511106064397346686568190500192457
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 331590515 ps: (rv_dm_ndmreset_req_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 331590515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:39) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
36.rv_dm_stress_all_with_rand_reset.90906077734307014110560016249551113161543644033297635244512127404236888565987
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2362006209 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2362006209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
42.rv_dm_stress_all_with_rand_reset.7498156134155709695840493230078647036224151770844364731917956191752815754048
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 779181679 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 779181679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 1 failures:
49.rv_dm_stress_all_with_rand_reset.52362650446563195102586566981019899185653156904871167382277487062138646001928
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 80907211 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 80907211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---