32d52b8d41
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 3.780s | 2.356ms | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.090s | 516.166us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.860s | 774.102us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 21.080s | 25.840ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 4.650s | 1.470ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 44.100s | 15.945ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 26.210s | 9.622ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.701m | 73.300ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.078m | 68.556ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 15.320s | 5.413ms | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 16.510s | 5.952ms | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.540s | 299.804us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.920s | 910.901us | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.510s | 310.091us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 5.900s | 2.082ms | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.240s | 181.678us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 2.720s | 728.429us | 2 | 2 | 100.00 |
V1 | progbuf_busy | rv_dm_progbuf_busy | 7.120s | 2.299ms | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.320s | 206.603us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.960s | 271.426us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.540s | 299.804us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.810s | 94.376us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.620s | 401.550us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.610s | 191.001us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.234m | 7.603ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.301m | 3.530ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.120s | 3.782ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.301m | 3.530ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.610s | 191.001us | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.780s | 47.203us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.940s | 141.001us | 5 | 5 | 100.00 |
V1 | TOTAL | 176 | 176 | 100.00 | |||
V2 | idcode | rv_dm_smoke | 3.780s | 2.356ms | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 2.930s | 1.990ms | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.770s | 89.547us | 2 | 2 | 100.00 |
V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.980s | 1.040ms | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 15.360s | 10.348ms | 20 | 20 | 100.00 |
rv_dm_delayed_resp_sba_tl_access | 35.700s | 11.719ms | 20 | 20 | 100.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 38.870s | 15.033ms | 20 | 20 | 100.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 3.443m | 131.101ms | 20 | 20 | 100.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.170s | 1.584ms | 2 | 2 | 100.00 |
V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
V2 | ndmreset_req | rv_dm_ndmreset_req | 3.050s | 2.199ms | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 0.930s | 194.461us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 27.330s | 8.850ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 6.970m | 150.000ms | 8 | 10 | 80.00 | ||
V2 | stress_all | rv_dm_stress_all | 2.536h | 10.000s | 15 | 50 | 30.00 |
V2 | alert_test | rv_dm_alert_test | 0.970s | 104.318us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.460s | 284.086us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.460s | 284.086us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.301m | 3.530ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.620s | 401.550us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.610s | 191.001us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.550s | 976.854us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.301m | 3.530ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.620s | 401.550us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.610s | 191.001us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.550s | 976.854us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 209 | 246 | 84.96 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 7.500s | 2.605ms | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 27.650s | 3.672ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.172m | 7.191ms | 0 | 50 | 0.00 |
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 410 | 497 | 82.49 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 28 | 28 | 28 | 100.00 |
V2 | 18 | 16 | 14 | 77.78 |
V2S | 10 | 2 | 2 | 20.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
77.95 | 94.66 | 79.12 | 86.17 | 71.79 | 84.67 | 98.52 | 30.69 |
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 17 failures:
2.rv_dm_stress_all.94407246100701498560117791090424509078405765540308951431689001234847023912332
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
Job ID: smart:d8735455-fc8f-43b9-b343-5f24ee215e6b
3.rv_dm_stress_all.103390718132721121266016092455666063554003539130000649955774409439070004708147
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
Job ID: smart:d9de6ff0-a183-4462-aff9-126a13f80163
... and 15 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 12 failures:
Test rv_dm_tap_fsm_rand_reset has 2 failures.
0.rv_dm_tap_fsm_rand_reset.11391612485349849686276422503680707137506407746293650879606372994073072307537
Line 384, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_tap_fsm_rand_reset.102969473217665420226718109666399022167316990957825163360980582716042628415223
Line 300, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 10 failures.
5.rv_dm_stress_all.61540930347756298747539451762687948649654905929356640049261344694694603197119
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all.104394559867097318027836749176779007511127265975310612053328030140473291851873
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 8 failures:
7.rv_dm_stress_all_with_rand_reset.55970895609257564982425027906848168472643289654439568352598033257411412837037
Line 289, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7190949676 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 7190949676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.98454652076397266964311840858203097666269083163202886477527287413320410183184
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 612503838 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 612503838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
24.rv_dm_stress_all.14177801821146174413841962870584057915438921746569586833592338260399469395730
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 23136164077 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 23136164077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.rv_dm_stress_all.66980736601763021677652947038235048014747168513730912319125575774591059078192
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 39274538477 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 39274538477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 6 failures:
2.rv_dm_stress_all_with_rand_reset.72226581164504120632505810320786459654743986632036318239251463217221153860809
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 544677952 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 544677952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_dm_stress_all_with_rand_reset.2273385545932357421184840729295819752928910079347549064172821900691053704844
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1641165396 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 1641165396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
47.rv_dm_stress_all.86256738546948716001284805067736934650669536642612125656354348673465090389922
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14401344544 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 14401344544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*)
has 6 failures:
9.rv_dm_stress_all.7930270810625073006446791963486968577501568987383075312369949092721409948316
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 4102551339 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x41d35100)
UVM_INFO @ 4102551339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all.21422968941536433787998977895520423966783744342756812488398515761289147879711
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 3886793250 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xe9025100)
UVM_INFO @ 3886793250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
10.rv_dm_stress_all_with_rand_reset.6671476758160401918095063761933690656676615193841989291741125374943941415884
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 6059650589 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xe67e3100)
UVM_INFO @ 6059650589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all_with_rand_reset.71112220570348392137182696262819972253482343459443365580987600374547381420140
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 7382347400 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xbbbda100)
UVM_INFO @ 7382347400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_*
has 4 failures:
5.rv_dm_stress_all_with_rand_reset.6947322937759387821191787993837345643220994950612790353696241992594993838393
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 807621097 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2450627859 [0x92119d13]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 807621097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all_with_rand_reset.72845979566369980359985166010536589775365363948332590174592181490844284992067
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1757650113 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1489982910 [0x58cf55be]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 1757650113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable
has 4 failures:
11.rv_dm_stress_all_with_rand_reset.86141075872126138205111725838450935320280041988208132060465772222525196684337
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 146892504 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 146892504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rv_dm_stress_all_with_rand_reset.76219346422040150204169401774321731310429584031968936742727152192620042597944
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 107403975 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 107403975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 4 failures:
12.rv_dm_stress_all_with_rand_reset.72255394436313722102755775638951486563150223365017177231921577184915900403563
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1007002952 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1007002952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all_with_rand_reset.52531499943526062578349957049925581323545896922620819683023788799800956175218
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1548062400 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1548062400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
has 4 failures:
15.rv_dm_stress_all_with_rand_reset.47507175004261700291461644942125759782940767540092305162531810772035885757004
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3187164525 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3527460994 [0xd240c882] vs 3526578818 [0xd2335282])
UVM_INFO @ 3187164525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all_with_rand_reset.180179343385508311205534694093328023728927543669701798527147977448008254032
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 184144458 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2026446889 [0x78c92029] vs 2026479472 [0x78c99f70])
UVM_INFO @ 184144458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen
has 4 failures:
21.rv_dm_stress_all_with_rand_reset.11535497657269779380198159098103791349999039871557514704666243656040879756160
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 175833889 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 175833889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_stress_all_with_rand_reset.53793859636851384300878198720633245641663274531066035967045313237106855821425
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 689193361 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 689193361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*])
has 3 failures:
0.rv_dm_stress_all_with_rand_reset.36903019109029469839012543089343317485958531118304879448606795561128896621494
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 216121087 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 216121087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.90522874183782731341486107732728081894358305465906785969446492956169859416721
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 484736658 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 484736658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
has 3 failures:
Test rv_dm_stress_all has 1 failures.
1.rv_dm_stress_all.16082242147893873861525954232122555504116096609997740074849431323266725887629
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 42952893738 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 42952893738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
38.rv_dm_stress_all_with_rand_reset.47390873692871719875551610095754329459686109961272562974908904600480070851114
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3179829636 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 3179829636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rv_dm_stress_all_with_rand_reset.32355047619191513509099590794026260963283749131682701402922313231897894204761
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 733848458 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 733848458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 3 failures:
1.rv_dm_stress_all_with_rand_reset.77952360576013009708621028668331416047140424264947593507673481844189195338548
Line 276, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5407758817 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (25 [0x19] vs 318780023 [0x13003277])
UVM_INFO @ 5407758817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.77971649918828814941794210375863364146430161829396521496670835529980576126308
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3487697602 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (6 [0x6] vs 1140886737 [0x44008cd1])
UVM_INFO @ 3487697602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*])
has 2 failures:
13.rv_dm_stress_all_with_rand_reset.28220618864660677641700123303690106185906127837454879093326212828981073350852
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 829557059 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (169 [0xa9] vs 0 [0x0])
UVM_INFO @ 829557059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.9702251791336889651287634052414862599948634082575190266137238532226994878470
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2770154762 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (199 [0xc7] vs 0 [0x0])
UVM_INFO @ 2770154762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 2 failures:
34.rv_dm_stress_all_with_rand_reset.65284517792310817498698186055118123562484470370739325543422277689615640851602
Line 271, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10322820413 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (21 [0x15] vs 897581077 [0x35800015])
UVM_INFO @ 10322820413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.rv_dm_stress_all_with_rand_reset.101946828050612002392971454104443049778631151549321370909028447027919501108460
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1142500690 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (21 [0x15] vs 3238002775 [0xc1000057])
UVM_INFO @ 1142500690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*])
has 2 failures:
39.rv_dm_stress_all_with_rand_reset.1573256914008142377810630020664477253346879356754912103713107589776103110666
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 483466247 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 483466247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_dm_stress_all_with_rand_reset.62137945052148950212633641150928917927673476575873896459263194851591677780894
Line 273, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2100376372 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2100376372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:228) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 1 failures:
3.rv_dm_stress_all_with_rand_reset.73937779900537355052035622468636018218731163681131913345059151785048006475959
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 838783683 ps: (rv_dm_base_vseq.sv:228) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 838783683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:51) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*])
has 1 failures:
8.rv_dm_stress_all_with_rand_reset.5119166486959098519336852710481998564680588133305767113369623086809328827994
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 996439154 ps: (rv_dm_ndmreset_req_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 996439154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:39) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*])
has 1 failures:
20.rv_dm_stress_all_with_rand_reset.110152802141909502472890073221406689710283139975474080644941975122091937307519
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3183686419 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3183686419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---