b29ffbb03c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.310s | 2.132ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.300s | 674.631us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 3.950s | 1.297ms | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 33.880s | 11.965ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 10.260s | 3.498ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 14.710s | 4.910ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 39.070s | 14.583ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 3.767m | 90.812ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.566m | 69.117ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 28.680s | 10.875ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 25.990s | 10.623ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.140s | 781.783us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 6.660s | 2.144ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.120s | 1.038ms | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 2.300s | 4.041ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.930s | 393.790us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 8.400s | 2.509ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.730s | 944.061us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.860s | 224.386us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.090s | 495.218us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.140s | 781.783us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.910s | 42.070us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.790s | 273.601us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.630s | 187.229us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 55.370s | 1.424ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.274m | 3.534ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 6.720s | 2.979ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.274m | 3.534ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.630s | 187.229us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.900s | 162.812us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.750s | 168.995us | 5 | 5 | 100.00 |
| V1 | TOTAL | 175 | 176 | 99.43 | |||
| V2 | idcode | rv_dm_smoke | 2.310s | 2.132ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.960s | 1.820ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.350s | 243.438us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.760s | 348.889us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 29.990s | 11.072ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 23.250s | 8.452ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 34.790s | 15.604ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 5.668m | 125.800ms | 19 | 20 | 95.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 4.280s | 1.248ms | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 2.390s | 608.879us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 3.010s | 1.059ms | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 9.440s | 5.961ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.530m | 56.103ms | 10 | 10 | 100.00 | ||
| V2 | stress_all | rv_dm_stress_all | 2.765h | 10.000s | 17 | 50 | 34.00 |
| V2 | alert_test | rv_dm_alert_test | 1.060s | 119.550us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.840s | 698.798us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.840s | 698.798us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.274m | 3.534ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.790s | 273.601us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.630s | 187.229us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.530s | 5.742ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.274m | 3.534ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.790s | 273.601us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.630s | 187.229us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.530s | 5.742ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 212 | 246 | 86.18 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.160s | 923.659us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 33.910s | 6.429ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 48.370s | 4.119ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 412 | 497 | 82.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 27 | 96.43 |
| V2 | 18 | 16 | 14 | 77.78 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 77.52 | 94.56 | 78.98 | 86.17 | 70.51 | 84.50 | 98.52 | 29.36 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:
Test rv_dm_stress_all has 14 failures.
0.rv_dm_stress_all.77497517175691869787092726889957589065358991735984429007334262888595492415559
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.6169980945660912853584287305588867705462244256449238137898330179466398540986
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Test rv_dm_jtag_dmi_csr_aliasing has 1 failures.
3.rv_dm_jtag_dmi_csr_aliasing.90326070014730146699287210958241692455013146058814530647540294717375127036171
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
15.rv_dm_autoincr_sba_tl_access.24274587716212693356176766565138434127779547562568818125566788077006874684037
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
3.rv_dm_stress_all.76056039684603946888108028507418284607803190574801897101346353891826985341116
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
Job ID: smart:9b204d3f-00ca-4662-b08d-557497790efc
4.rv_dm_stress_all.40924830659292751156683471597190151198833782484318625249430267248644166623661
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
Job ID: smart:1f42aa10-ce60-414a-870f-52ac0d30bf84
... and 12 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 9 failures:
3.rv_dm_stress_all_with_rand_reset.94677134453641915448822076886213710883504085688936326048199132817311453661730
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 299911784 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 299911784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.6643832719854977041921357395804857079367537333712812016425452984164499244380
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 322964825 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 322964825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
6.rv_dm_stress_all.62718439427639728581795469218429876477309444840602261580959769458340914119100
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8343470984 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 8343470984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all.3361008446128585575807670442190324461096185244579026448154162618240129460560
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6939320957 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 6939320957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 8 failures:
5.rv_dm_stress_all_with_rand_reset.94153848783555571548563977421209985095792238208413288587535015727374975111480
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 516209869 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1114913124 [0x42743964]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 516209869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.9326333736445038050846385955613958268449793314041112793405082406401959465378
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2363750678 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 722928720 [0x2b170450]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 2363750678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 6 failures:
0.rv_dm_stress_all_with_rand_reset.102131373441171291675535619657267455647444554544716197350637295780337951439071
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 6061575238 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 6061575238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all_with_rand_reset.108638859796493148657508004120662840363008924300757017609975469468156009898499
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3307998854 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 3307998854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 6 failures:
13.rv_dm_stress_all_with_rand_reset.66788327383454390510553947354883923890360282130277614911619202213924118626118
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2388430640 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 2388430640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all_with_rand_reset.18125564126687471090262362517578625070551041657298966349441106699990882969256
Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5664430876 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 5664430876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
40.rv_dm_stress_all.107090847326866222963589904146610617051688094933528367860022004488974895888220
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 40733169707 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 40733169707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 5 failures:
1.rv_dm_stress_all_with_rand_reset.107498511567472005833358227328307704680141520327665411797360403162550036694448
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1626494966 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 3791558014 [0xe1fe957e])
UVM_INFO @ 1626494966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_stress_all_with_rand_reset.55340392610301343007230482207792068937681593807681340427498839765728950936789
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 861720388 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (976200716 [0x3a2fa40c] vs 318300179 [0x12f8e013])
UVM_INFO @ 861720388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 5 failures:
27.rv_dm_stress_all_with_rand_reset.77331386443151919855823631139264257333515182188938925709174958854450380046667
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 410272123 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (3 [0x3] vs 305552387 [0x12365c03])
UVM_INFO @ 410272123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rv_dm_stress_all_with_rand_reset.84670631173553923154674166138688792266938096270682210651162619470027229777851
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 844784545 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (6 [0x6] vs 4026531941 [0xf0000065])
UVM_INFO @ 844784545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 3 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
7.rv_dm_stress_all_with_rand_reset.66014074611917413321075735874027096078317389668829088351499216849012377086174
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 655433366 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 655433366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
13.rv_dm_stress_all.46403163271237130948709411559918455880598701919710504359975093240541826481340
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7708038617 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7708038617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_dm_stress_all.43596644278485766134266029272576675084180826552468525165318700421269704516352
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2568063555 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 2568063555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
9.rv_dm_stress_all_with_rand_reset.85367796591471874292325079054164358343800065717422536793941594181424155737135
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1083324584 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1083324584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.rv_dm_stress_all_with_rand_reset.89903241402824168788374604170123041385381550104536819725156708278078702551038
Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2818507924 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2818507924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 2 failures:
18.rv_dm_stress_all_with_rand_reset.112785505817074332742793228302109483920508720339721944894895530300057912665143
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5132293426 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (13901312 [0xd41e00] vs 0 [0x0])
UVM_INFO @ 5132293426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all_with_rand_reset.61350969655213205927811405739003216324355946660496429509982590150859552270229
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2077585294 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (1728053248 [0x67000000] vs 0 [0x0])
UVM_INFO @ 2077585294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 2 failures:
22.rv_dm_stress_all_with_rand_reset.16384340969056675436467731875656981534856359584472308229714275523721238109642
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2688366029 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x695b0100)
UVM_INFO @ 2688366029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_dm_stress_all_with_rand_reset.88282555506913193599083175179293828136036213855167482309244145531566709959310
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4285981897 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x42f92100)
UVM_INFO @ 4285981897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
2.rv_dm_stress_all_with_rand_reset.90844204204500275819795838312807071388548601900784397677833695345394395084245
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1437614629 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1437614629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:36) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
4.rv_dm_stress_all_with_rand_reset.9992874313026659549434901927245434601493540418456211733230562587457164605805
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 662469093 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 662469093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 1 failures:
11.rv_dm_stress_all_with_rand_reset.37795736676480852201645567198333487394949890792394356765745918783189312658689
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4096995406 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 4096995406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:24) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
17.rv_dm_stress_all_with_rand_reset.8679528262270779985866346681283751171816982765968926105722814343815135355638
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 839483604 ps: (rv_dm_mem_tl_access_halted_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 839483604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:51) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
26.rv_dm_stress_all_with_rand_reset.77661975943207134192695760620548533112730197220989309784125212819829531526422
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3265078200 ps: (rv_dm_ndmreset_req_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (2958143569 [0xb051b051] vs 1483802000 [0x58710590])
UVM_INFO @ 3265078200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:39) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
33.rv_dm_stress_all_with_rand_reset.64746513586029149426072280156852014723756757253493312207240141148780807111018
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1450169331 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1450169331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:31) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
44.rv_dm_stress_all_with_rand_reset.41904786042942541709868413052438617306524402588595026132534633736784227545233
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1953446142 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata2 (11 [0xb] vs 2958143569 [0xb051b051])
UVM_INFO @ 1953446142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---