RV_DM Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.870s	2.093ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	4.470s	1.389ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.190s	927.535us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	58.880s	43.819ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.100s	953.353us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	38.250s	14.535ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	39.830s	15.287ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.061m	46.615ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	5.129m	111.050ms	3	5	60.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	40.220s	36.383ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	20.340s	7.085ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	14.020s	5.080ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	9.900s	3.312ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.650s	365.934us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.900s	841.561us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.640s	329.340us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.850s	1.495ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	6.760s	2.328ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.050s	143.236us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.950s	170.359us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	14.020s	5.080ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.010s	77.751us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.490s	514.288us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.680s	217.663us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	54.530s	7.389ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.247m	3.487ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.580s	4.437ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.247m	3.487ms	5	5	100.00
		rv_dm_csr_rw	2.680s	217.663us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.850s	112.605us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.880s	94.152us	5	5	100.00
V1		TOTAL			174	176	98.86
V2	idcode	rv_dm_smoke	6.870s	2.093ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.620s	1.267ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.820s	101.852us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.580s	1.899ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	14.170s	5.056ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	17.110s	11.946ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	36.620s	12.979ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.138m	118.541ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	8.500s	2.911ms	2	2	100.00
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	6.000s	3.726ms	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.240s	534.428us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	10.220s	5.779ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.770m	57.959ms	10	10	100.00
V2	stress_all	rv_dm_stress_all	2.467h	10.000s	16	50	32.00
V2	alert_test	rv_dm_alert_test	1.090s	162.603us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.950s	238.278us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.950s	238.278us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.247m	3.487ms	5	5	100.00
		rv_dm_csr_hw_reset	3.490s	514.288us	5	5	100.00
		rv_dm_csr_rw	2.680s	217.663us	20	20	100.00
		rv_dm_same_csr_outstanding	8.630s	1.148ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.247m	3.487ms	5	5	100.00
		rv_dm_csr_hw_reset	3.490s	514.288us	5	5	100.00
		rv_dm_csr_rw	2.680s	217.663us	20	20	100.00
		rv_dm_same_csr_outstanding	8.630s	1.148ms	20	20	100.00
V2		TOTAL			212	246	86.18
V2S	tl_intg_err	rv_dm_sec_cm	2.380s	2.226ms	5	5	100.00
		rv_dm_tl_intg_err	21.670s	1.649ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	4.736m	33.095ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			411	497	82.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	27	96.43
V2	18	16	15	83.33
V2S	10	2	2	20.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
79.04	94.56	78.90	86.17	71.79	84.50	98.52	38.82

Failure Buckets

Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rv_dm_stress_all has 17 failures.
  - 0.rv_dm_stress_all.85334194521881995845327255310829545471395260575256370865893117652173806866737
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:bc2c0fef-4912-450a-8971-5c5d86ab7e3b
```
  - 2.rv_dm_stress_all.65272757256682762199051994345268757482034355524768550569450481660100393289416
    Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
```
  Job ID: smart:d8c083ca-4e29-4303-8eef-04bc79fa7b52
```
  - ... and 15 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 14 failures:
- Test rv_dm_jtag_dmi_csr_aliasing has 2 failures.
  - 0.rv_dm_jtag_dmi_csr_aliasing.59927234691502962397102690938223572628051900923895611549240982262220906650443
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_jtag_dmi_csr_aliasing.35901646410518135491322990054266915544158222250775393072543077100244093553939
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 12 failures.
  - 6.rv_dm_stress_all.61531740735527362107636708251306360741528227204790748011594661467461432311179
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rv_dm_stress_all.9140785346323358889837654210403408704391585385565394430442893059573613452448
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 9 failures:

Test rv_dm_stress_all_with_rand_reset has 8 failures.

0.rv_dm_stress_all_with_rand_reset.27349954176745806069207045273043883573047330427967420560176293408511722315953
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2926334729 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 2926334729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rv_dm_stress_all_with_rand_reset.85603241384596506907312569017070804177432560198719339782891347902465064870551
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 754830374 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
  UVM_INFO @ 754830374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test rv_dm_stress_all has 1 failures.

33.rv_dm_stress_all.95145807500252668494294758580574259345258644424640502398351817470669569845807
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 20811268968 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 20811268968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 8 failures:
- Test rv_dm_stress_all_with_rand_reset has 8 failures.
  - 10.rv_dm_stress_all_with_rand_reset.30823976807888243437513284943500530701472726533243077732942255696421257113050
    Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 8796877824 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 8796877824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.rv_dm_stress_all_with_rand_reset.40632539253020966722758771597967804964202420745216047840064839293079041242978
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 309847980 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 309847980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 7 failures:
- Test rv_dm_stress_all_with_rand_reset has 7 failures.
  - 1.rv_dm_stress_all_with_rand_reset.51270077865701814896841152836814843972906723900095966881544428303631878429876
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2676805703 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1482148893 [0x5857cc1d]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 2676805703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.151830226852931372601928931675757743552546245082938598314198396348175621660
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 755142235 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 1376846948 [0x52110464]) reg name: rv_dm_mem_reg_block.dataaddr_1
  UVM_INFO @ 755142235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 7 failures:
- Test rv_dm_stress_all_with_rand_reset has 7 failures.
  - 6.rv_dm_stress_all_with_rand_reset.94539908267364117734161447423417675442312127138844594786427486895645645194482
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 211101281 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @ 211101281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.56399494488786420571027391343991605279861596848249090646534257118995631074583
    Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14087549367 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
  UVM_INFO @ 14087549367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 4 failures:
- Test rv_dm_stress_all has 3 failures.
  - 25.rv_dm_stress_all.89604055735401103745355054160063597103559209914013491677078945345192321559281
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 38947281823 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 38947281823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.rv_dm_stress_all.73265857644515465528636377143553653028045794945336638624664906920933063837677
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 17665548313 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 17665548313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 26.rv_dm_stress_all_with_rand_reset.75626423879305580536724453235733916477027042009743280618284703423137323312269
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 672111487 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 672111487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 2.rv_dm_stress_all_with_rand_reset.101953429798404411219374666475691384116194697479529980153891169208067717684088
    Line 285, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4630487156 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (27852 [0x6ccc] vs 0 [0x0])
  UVM_INFO @ 4630487156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rv_dm_stress_all_with_rand_reset.34566263759540259250109900421677508858575780170800678195432578670196676470975
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2170606082 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (155 [0x9b] vs 0 [0x0])
  UVM_INFO @ 2170606082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 3.rv_dm_stress_all_with_rand_reset.37833804406093823507217063146871234923673985075753027370611553521778153125362
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1623409202 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 1623409202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rv_dm_stress_all_with_rand_reset.58355383626033215861352536119152445487393409614487473133285620576034104686960
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 589454244 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
  UVM_INFO @ 589454244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 11.rv_dm_stress_all_with_rand_reset.46590477520389539267830741972226086718282356152319454904409310651472630207498
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 475011270 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (8 [0x8] vs 9765902 [0x95040e])
  UVM_INFO @ 475011270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.rv_dm_stress_all_with_rand_reset.59758420006265462841703573027103267626967952568071119114018217925831658342222
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 345102526 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (6 [0x6] vs 67 [0x43])
  UVM_INFO @ 345102526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 24.rv_dm_stress_all_with_rand_reset.38257931645834736118588184352022953405069877249053869462378739264192449557471
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6824086062 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xf4f4d100)
  UVM_INFO @ 6824086062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.rv_dm_stress_all_with_rand_reset.54220087947669915508123235796987689392280250341063569515616542906609057996574
    Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11025888745 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x20f1100)
  UVM_INFO @ 11025888745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 40.rv_dm_stress_all.68324373821083208155216996990532702564999882947834817497329831274168372558882
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 3467561257 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x53f2e100)
  UVM_INFO @ 3467561257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all_with_rand_reset has 3 failures.

28.rv_dm_stress_all_with_rand_reset.50008436678270893909405254480985477676114919613334683582507773572744400210361
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 570290861 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3020102371 [0xb4031ae3] vs 3020113820 [0xb403479c])
  UVM_INFO @ 570290861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.rv_dm_stress_all_with_rand_reset.53110072248233845306712582415868623745781586243894558788339621296832067250556
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 476433985 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2441406836 [0x9184e974] vs 1132771761 [0x4384b9b1])
  UVM_INFO @ 476433985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 5.rv_dm_stress_all_with_rand_reset.93261350961718495688551996841873216083083573729776476208169669186951852765310
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157019083 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (11 [0xb] vs 0 [0x0])
  UVM_INFO @ 157019083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rv_dm_stress_all_with_rand_reset.22536104098000587775206812240801905077662449758622335013825914451498459939276
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 775495902 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (9 [0x9] vs 38733 [0x974d])
  UVM_INFO @ 775495902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 16.rv_dm_stress_all_with_rand_reset.8973045164537511591257651189445693475249156960708908800192026398659296138349
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 631706667 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 631706667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.rv_dm_stress_all_with_rand_reset.78758930330519701656688856827046291477878769279867874253874562575429027790557
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4911524695 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4911524695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:39) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 23.rv_dm_stress_all_with_rand_reset.10928405073569283753402181449301785957319582937774431436106503356612832378650
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1205136836 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 1205136836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```