8fdb25c8d9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 8.120s | 3.644ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 3.140s | 947.490us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.310s | 686.313us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 59.810s | 22.986ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.620s | 788.991us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 17.240s | 25.257ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 19.660s | 7.571ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 4.417m | 98.966ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.840m | 85.512ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 36.800s | 23.589ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 10.600s | 13.156ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.420s | 1.018ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.430s | 1.377ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.890s | 916.371us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.980s | 1.273ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.620s | 365.568us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.650s | 2.867ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 3.050s | 1.893ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.970s | 116.745us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.150s | 176.920us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.420s | 1.018ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.860s | 136.499us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.460s | 471.158us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.550s | 193.584us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.208m | 30.432ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.319m | 19.474ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 12.360s | 6.235ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.319m | 19.474ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.550s | 193.584us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.920s | 116.148us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.890s | 113.232us | 5 | 5 | 100.00 |
| V1 | TOTAL | 176 | 176 | 100.00 | |||
| V2 | idcode | rv_dm_smoke | 8.120s | 3.644ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.970s | 587.962us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.280s | 242.803us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 8.320s | 3.003ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 32.020s | 13.258ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 35.340s | 12.063ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 29.730s | 9.896ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 5.665m | 153.327ms | 20 | 20 | 100.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.510s | 1.128ms | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 3.430s | 3.202ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.200s | 616.977us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 6.240s | 3.327ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 3.993m | 300.000ms | 9 | 10 | 90.00 | ||
| V2 | stress_all | rv_dm_stress_all | 2.236h | 10.000s | 16 | 50 | 32.00 |
| V2 | alert_test | rv_dm_alert_test | 1.100s | 167.237us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.750s | 975.390us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.750s | 975.390us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.319m | 19.474ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.460s | 471.158us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.550s | 193.584us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.070s | 686.612us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.319m | 19.474ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.460s | 471.158us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.550s | 193.584us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.070s | 686.612us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 210 | 246 | 85.37 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.070s | 432.166us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 21.390s | 2.422ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.078m | 6.005ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 411 | 457 | 89.93 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 28 | 100.00 |
| V2 | 18 | 16 | 13 | 72.22 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 79.32 | 94.71 | 79.17 | 88.43 | 71.79 | 84.83 | 98.52 | 37.74 |
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
1.rv_dm_stress_all.50424912198917348573041280960185156602778556204774110553329381433793532520302
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
Job ID: smart:8a891fa4-2581-41f0-aa3e-713b82d219a4
3.rv_dm_stress_all.73003666674074120070232658587007775279072831528015372952929355042879264212819
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
Job ID: smart:9892b950-3b3c-4d10-89fd-7236bc6ee2e4
... and 15 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
Test rv_dm_tap_fsm_rand_reset has 1 failures.
5.rv_dm_tap_fsm_rand_reset.90545099524739803187093096308410786269958194222731657805639588598223906407251
Line 343, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 7 failures.
12.rv_dm_stress_all.94819354500010731581177153303619183086080857900994501495308051721881216710375
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all.38142903984599599983236615759386950642241369593104777257715621956663790105218
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 5 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
6.rv_dm_stress_all_with_rand_reset.44974504853314144984417099326439966642520994649100397813563941969770638938329
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4902097389 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x9580e100)
UVM_INFO @ 4902097389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 4 failures.
8.rv_dm_stress_all.73328705319536339841321972397538810350284047379680053494854531436322745125193
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 4767312956 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x6501f100)
UVM_INFO @ 4767312956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all.71612750267783433761093458340495837229284369680241227354337010386899802129284
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 3563803479 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x286eb100)
UVM_INFO @ 3563803479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 3 failures:
1.rv_dm_stress_all_with_rand_reset.6117697933764674657347176567471871693902023126895029593419440370362418611657
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 854824046 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 854824046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.83126799888531256527925954368520735843999512308660009904369576352473692364411
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1080751764 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 1080751764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 2 failures:
4.rv_dm_stress_all_with_rand_reset.86023142582286219334752514195127862619591801990680242563004698810115669448461
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3004328690 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 412039465 [0x188f3929]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 3004328690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.90449018861863488093573512433964970837883980996144546078993747217218940994852
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1005455775 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 180493553 [0xac21cf1]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 1005455775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:208) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
7.rv_dm_stress_all_with_rand_reset.53968810036944361799543521127129198540858432012680277451996772515372176228615
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 478384216 ps: (rv_dm_base_vseq.sv:208) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 478384216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
43.rv_dm_stress_all.75473897738528581762503135510024294887787287699255591518914786583403095765033
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 27302753469 ps: (rv_dm_base_vseq.sv:208) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 27302753469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 2 failures:
25.rv_dm_stress_all.23588524855504121760310718668751525058557375711961384365704107781085783473881
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 15023290589 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 15023290589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all.103559540510108161859059966015919971058049079334585027017373054047967398569859
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3446483915 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 3446483915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
33.rv_dm_stress_all.66984907102875197611264846191599833119970219448327636096715667828263299596468
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7162929718 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 2958143569 [0xb051b051])
UVM_INFO @ 7162929718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all.62759481671296608338594474381977999882518033415302162760185572485391537088086
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14471000302 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (13 [0xd] vs 2958143569 [0xb051b051])
UVM_INFO @ 14471000302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
0.rv_dm_tap_fsm.86727959369942594278063902507362277932741367477062213823503461499645407506088
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
UVM_ERROR @ 3326751079 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 3883646125 [0xe77bbcad])
UVM_INFO @ 3326751079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
0.rv_dm_stress_all_with_rand_reset.102416986237917846043465934777208849874019059668850957545350283669764434631495
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1990522746 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1065137269 [0x3f7cb475] vs 295482485 [0x119cb475])
UVM_INFO @ 1990522746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:208) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 1 failures:
3.rv_dm_stress_all_with_rand_reset.45821841820316720958120895364282701149808226084361171603041063517417935841541
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4524979081 ps: (rv_dm_base_vseq.sv:208) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 4524979081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
5.rv_dm_stress_all_with_rand_reset.5606842211298421747906818160741315684516323671716883948919276655115019904375
Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6004957755 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6004957755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
39.rv_dm_stress_all.29186213144200814693881292805671227684520580113285141023537777385428585802119
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 18166074200 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 18166074200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---