RV_DM Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 8.120s 3.644ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.140s 947.490us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.310s 686.313us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 59.810s 22.986ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.620s 788.991us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 17.240s 25.257ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 19.660s 7.571ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.417m 98.966ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.840m 85.512ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 36.800s 23.589ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 10.600s 13.156ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.420s 1.018ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.430s 1.377ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.890s 916.371us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.980s 1.273ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.620s 365.568us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.650s 2.867ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 3.050s 1.893ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.970s 116.745us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.150s 176.920us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.420s 1.018ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.860s 136.499us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.460s 471.158us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.550s 193.584us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.208m 30.432ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.319m 19.474ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 12.360s 6.235ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.319m 19.474ms 5 5 100.00
rv_dm_csr_rw 2.550s 193.584us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.920s 116.148us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.890s 113.232us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 8.120s 3.644ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.970s 587.962us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.280s 242.803us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 8.320s 3.003ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 32.020s 13.258ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 35.340s 12.063ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 29.730s 9.896ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 5.665m 153.327ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.510s 1.128ms 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 3.430s 3.202ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.200s 616.977us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.240s 3.327ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 3.993m 300.000ms 9 10 90.00
V2 stress_all rv_dm_stress_all 2.236h 10.000s 16 50 32.00
V2 alert_test rv_dm_alert_test 1.100s 167.237us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.750s 975.390us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.750s 975.390us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.319m 19.474ms 5 5 100.00
rv_dm_csr_hw_reset 2.460s 471.158us 5 5 100.00
rv_dm_csr_rw 2.550s 193.584us 20 20 100.00
rv_dm_same_csr_outstanding 8.070s 686.612us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.319m 19.474ms 5 5 100.00
rv_dm_csr_hw_reset 2.460s 471.158us 5 5 100.00
rv_dm_csr_rw 2.550s 193.584us 20 20 100.00
rv_dm_same_csr_outstanding 8.070s 686.612us 20 20 100.00
V2 TOTAL 210 246 85.37
V2S tl_intg_err rv_dm_sec_cm 2.070s 432.166us 5 5 100.00
rv_dm_tl_intg_err 21.390s 2.422ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.078m 6.005ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 411 457 89.93

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 16 13 72.22
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.32 94.71 79.17 88.43 71.79 84.83 98.52 37.74

Failure Buckets

Past Results