548a3880d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.970s | 1.342ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 4.280s | 1.614ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 3.220s | 858.926us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 36.420s | 16.380ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.800s | 2.114ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 23.780s | 9.848ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 40.660s | 15.559ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.764m | 58.836ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.260m | 150.000ms | 3 | 5 | 60.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 24.000s | 32.709ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 22.390s | 12.943ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 11.070s | 3.958ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 12.110s | 4.210ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.460s | 306.892us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.420s | 2.288ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.110s | 291.465us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 3.000s | 2.455ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 4.020s | 2.393ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.460s | 283.509us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 3.260s | 1.054ms | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 11.070s | 3.958ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.940s | 54.454us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.600s | 139.270us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.660s | 189.926us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.157m | 69.974ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.257m | 15.502ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.580s | 3.550ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.257m | 15.502ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.660s | 189.926us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.880s | 95.837us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 1.030s | 153.935us | 5 | 5 | 100.00 |
| V1 | TOTAL | 174 | 176 | 98.86 | |||
| V2 | idcode | rv_dm_smoke | 1.970s | 1.342ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.580s | 1.368ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.140s | 363.422us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 7.310s | 2.701ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 44.420s | 15.399ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 13.900s | 5.183ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 21.850s | 8.325ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 6.432m | 143.591ms | 19 | 20 | 95.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 3.470s | 1.786ms | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 11.880s | 4.437ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.720s | 814.832us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 27.270s | 12.502ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.972m | 42.604ms | 10 | 10 | 100.00 | ||
| V2 | stress_all | rv_dm_stress_all | 2.070h | 10.000s | 15 | 50 | 30.00 |
| V2 | alert_test | rv_dm_alert_test | 0.910s | 124.425us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.440s | 360.664us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.440s | 360.664us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.257m | 15.502ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.600s | 139.270us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.660s | 189.926us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.540s | 3.131ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.257m | 15.502ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.600s | 139.270us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.660s | 189.926us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.540s | 3.131ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 210 | 246 | 85.37 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.020s | 777.146us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 28.930s | 7.583ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 2.266m | 84.777ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 409 | 497 | 82.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 27 | 96.43 |
| V2 | 18 | 16 | 14 | 77.78 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 78.72 | 94.56 | 78.90 | 86.17 | 71.79 | 84.50 | 98.31 | 36.80 |
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
0.rv_dm_stress_all.106304410105895964137094910792194040841873548269613761425305431763460227855808
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
Job ID: smart:ee81d595-6f5b-4f19-82ef-a17148e561c8
3.rv_dm_stress_all.114769334789107355686776056934289655463441882019800705269927162785128970573766
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
Job ID: smart:ce00fa48-3537-44e2-af24-9098cbea1e26
... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
Test rv_dm_jtag_dmi_csr_aliasing has 2 failures.
2.rv_dm_jtag_dmi_csr_aliasing.38941872565061882107537601080616270603355649812209837219958851083733629214270
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_jtag_dmi_csr_aliasing.52267789707949897408113144093925535789319948453170764180650728741618019789794
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 9 failures.
5.rv_dm_stress_all.6723777496518896469863513172956169325358121508817507707309153614654531851887
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_stress_all.90401940198695670106977046219878129898284666784018444147268645680022084495246
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test rv_dm_autoincr_sba_tl_access has 1 failures.
15.rv_dm_autoincr_sba_tl_access.36705919859950326265978402420586002575764162171471224342264157465164824998298
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 150000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 150000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 150000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 7 failures:
8.rv_dm_stress_all_with_rand_reset.86167177574987037927512356915440917530804793463210308921610005720197201830162
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 378130216 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 378130216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.24572102056773497306150392285194276729743106035684996978880715536026925595833
Line 276, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2343741900 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 2343741900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
36.rv_dm_stress_all.61828673629395651000728143770526981005091628866509049587791409923707895535487
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 48275291901 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 48275291901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 6 failures:
2.rv_dm_stress_all_with_rand_reset.106324441951775704576162930747449176675800840763404363740359880383606151990984
Line 318, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 84776864373 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 84776864373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.54612060109096139505877785404583125834537574198695984100231404549541611744042
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1398022085 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 1398022085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 5 failures:
3.rv_dm_stress_all_with_rand_reset.27978868072223572492125000107906925545502059539325335688224701707704600608941
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1942601896 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2450638512 [0x9211c6b0]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 1942601896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_stress_all_with_rand_reset.17468933059185953015957326312952834935389142173070759400524275179089730513321
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 390582199 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2844525648 [0xa98c0450]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 390582199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 5 failures:
Test rv_dm_stress_all has 2 failures.
7.rv_dm_stress_all.9915141922435213354374419784541805721644765717486713675250237890862239379237
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 25992906849 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 2318817479 [0x8a3658c7])
UVM_INFO @ 25992906849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all.33619795216943705673009913731723769796611931303169570666508647246744408452970
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 22121075216 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 2763016593 [0xa4b04991])
UVM_INFO @ 22121075216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 3 failures.
16.rv_dm_stress_all_with_rand_reset.63170771839612576486090785658560411354349236497986544922014096049279933547342
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 286631297 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1011606807 [0x3c4be517] vs 1011551238 [0x3c4b0c06])
UVM_INFO @ 286631297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.rv_dm_stress_all_with_rand_reset.22031380384655710391174581543160395266367051925088954137900843360880502657972
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 889892242 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 2714337793 [0xa1c98201])
UVM_INFO @ 889892242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 4 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
0.rv_dm_stress_all_with_rand_reset.94384698200572506623060431724826224394715403642763727735917542785968561842284
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1058586406 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 1058586406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 3 failures.
12.rv_dm_stress_all.101648487731801601011917060880393036648416286336098110451643470356238469693849
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14914610160 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 14914610160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all.10169429794938527549329674113959274309112868710659077312243464538558254461287
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2249826934 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 2249826934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
7.rv_dm_stress_all_with_rand_reset.7158095209492605986854864225110736445544499116250098988524725655417495246961
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 570506393 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 570506393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all_with_rand_reset.45143314252099200450768864322025715569682277545913974085497095723951883243661
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1055927750 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1055927750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:203) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
20.rv_dm_stress_all_with_rand_reset.60529126718081580895778616849147602394747269542738267431158980749154006679030
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3236456907 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 3236456907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rv_dm_stress_all_with_rand_reset.41783184978284468137965033156308936346494363593834480421508838918404242287663
Line 285, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4262373511 ps: (rv_dm_base_vseq.sv:203) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 4262373511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:38) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 4 failures:
22.rv_dm_stress_all_with_rand_reset.115519068566878473963754533685410459640163341066984203280381479779921325617761
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 407345933 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 407345933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rv_dm_stress_all_with_rand_reset.9729424896883942650263833955289545919766402104739936761212368513488640619137
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2396262284 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2396262284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 3 failures:
1.rv_dm_stress_all_with_rand_reset.76163500798625432901611433563978246337481772315244401341851830847063245728450
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 184455772 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 184455772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all_with_rand_reset.16660363266613585216996941774854488375111032471775377585968207622654912989751
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 908281932 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 908281932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
29.rv_dm_stress_all_with_rand_reset.110399069517349156842896670147152607650489720330269533036645541037601131975350
Line 316, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9572409083 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 9572409083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_dm_stress_all_with_rand_reset.73510884878900872776765092903008745488899671747646616903241382682084772697382
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 432135283 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 432135283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 2 failures:
Test rv_dm_stress_all has 1 failures.
1.rv_dm_stress_all.81589995563185615076237268027244002324443429479554378096096686787059184842470
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10347855876 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 10347855876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
41.rv_dm_stress_all_with_rand_reset.637857655914571200868080810147411998145652494489858143920853454365907394844
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1278272179 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (8900889 [0x87d119] vs 0 [0x0])
UVM_INFO @ 1278272179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 2 failures:
5.rv_dm_stress_all_with_rand_reset.74322609867466284880383108809283948728435567076000521110321966148442537900243
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4786896198 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xc12a1100)
UVM_INFO @ 4786896198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.rv_dm_stress_all_with_rand_reset.109756774516947516660106023231518463637667786589605770504859126378510260278908
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 7055086993 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x8640a100)
UVM_INFO @ 7055086993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
6.rv_dm_stress_all_with_rand_reset.19083112029109292451836117021564225745150391056784123256644634366740846920676
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2013013130 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (13 [0xd] vs 15728848 [0xf000d0])
UVM_INFO @ 2013013130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.10172754788923175808157647318375544111995158120634799168709810635483784804990
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 961350669 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (22 [0x16] vs 1899692106 [0x713b004a])
UVM_INFO @ 961350669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:39) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 2 failures:
17.rv_dm_stress_all_with_rand_reset.48987528124906832376026462433954983495701863595372833112024444434076602047763
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1935196793 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 2 [0x2])
UVM_INFO @ 1935196793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.rv_dm_stress_all_with_rand_reset.49976893932170783908635813058566671903519284066712330535602426542632895099329
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1578696118 ps: (rv_dm_halt_resume_whereto_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1578696118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:24) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
13.rv_dm_stress_all_with_rand_reset.1543152987190072093095639766002811052904032373044858394073938339661655466365
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1914036896 ps: (rv_dm_mem_tl_access_halted_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1914036896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all_with_rand_reset.109632062801224234280192950274306866259260658289753474282601441665468668337957
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1714545474 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (27 [0x1b] vs 93497627 [0x592a91b])
UVM_INFO @ 1714545474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:228) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
24.rv_dm_stress_all_with_rand_reset.89971541580406258184527831878294981529823890378945437202189211820692935654809
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126436742 ps: (rv_dm_base_vseq.sv:228) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126436742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:36) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
48.rv_dm_stress_all_with_rand_reset.51725332047048107034862531126348878662574137117676465586960292295777494273086
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3597778620 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3597778620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---