RV_DM Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.970s 1.342ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 4.280s 1.614ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.220s 858.926us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 36.420s 16.380ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.800s 2.114ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 23.780s 9.848ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 40.660s 15.559ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.764m 58.836ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.260m 150.000ms 3 5 60.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 24.000s 32.709ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 22.390s 12.943ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 11.070s 3.958ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 12.110s 4.210ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.460s 306.892us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.420s 2.288ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.110s 291.465us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 3.000s 2.455ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 4.020s 2.393ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.460s 283.509us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 3.260s 1.054ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 11.070s 3.958ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.940s 54.454us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.600s 139.270us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.660s 189.926us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.157m 69.974ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.257m 15.502ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 9.580s 3.550ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.257m 15.502ms 5 5 100.00
rv_dm_csr_rw 2.660s 189.926us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.880s 95.837us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.030s 153.935us 5 5 100.00
V1 TOTAL 174 176 98.86
V2 idcode rv_dm_smoke 1.970s 1.342ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.580s 1.368ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.140s 363.422us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 7.310s 2.701ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 44.420s 15.399ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 13.900s 5.183ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 21.850s 8.325ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 6.432m 143.591ms 19 20 95.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 3.470s 1.786ms 2 2 100.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 11.880s 4.437ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.720s 814.832us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 27.270s 12.502ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.972m 42.604ms 10 10 100.00
V2 stress_all rv_dm_stress_all 2.070h 10.000s 15 50 30.00
V2 alert_test rv_dm_alert_test 0.910s 124.425us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.440s 360.664us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.440s 360.664us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.257m 15.502ms 5 5 100.00
rv_dm_csr_hw_reset 2.600s 139.270us 5 5 100.00
rv_dm_csr_rw 2.660s 189.926us 20 20 100.00
rv_dm_same_csr_outstanding 8.540s 3.131ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.257m 15.502ms 5 5 100.00
rv_dm_csr_hw_reset 2.600s 139.270us 5 5 100.00
rv_dm_csr_rw 2.660s 189.926us 20 20 100.00
rv_dm_same_csr_outstanding 8.540s 3.131ms 20 20 100.00
V2 TOTAL 210 246 85.37
V2S tl_intg_err rv_dm_sec_cm 2.020s 777.146us 5 5 100.00
rv_dm_tl_intg_err 28.930s 7.583ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.266m 84.777ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 409 497 82.29

Testplan Progress

Items Total Written Passing Progress
V1 28 28 27 96.43
V2 18 16 14 77.78
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.72 94.56 78.90 86.17 71.79 84.50 98.31 36.80

Failure Buckets

Past Results