Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.16	100.00	85.71	97.60		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	186393130	1425660	0	0
late_debug_enable_rd_A	186393130	109518	0	0
late_debug_enable_regwen_rd_A	186393130	93884	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186393130	1425660	0	0
T26	537084	170653	0	0
T49	199467	43842	0	0
T55	235151	37293	0	0
T65	201740	66786	0	0
T80	478494	101152	0	0
T81	850607	160973	0	0
T99	733559	233987	0	0
T100	877928	279147	0	0
T101	158140	278775	0	0
T102	21175	530	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186393130	109518	0	0
T101	158140	92662	0	0
T109	247502	210	0	0
T110	61848	28	0	0
T112	14310	7	0	0
T144	28371	84	0	0
T145	243146	48	0	0
T146	16405	59	0	0
T147	18450	82	0	0
T148	15563	46	0	0
T149	19949	58	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186393130	93884	0	0
T101	158140	81231	0	0
T109	247502	206	0	0
T110	61848	65	0	0
T112	14310	2	0	0
T144	28371	70	0	0
T145	243146	35	0	0
T146	16405	67	0	0
T147	18450	109	0	0
T148	15563	34	0	0
T149	19949	74	0	0