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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
 dap 84.46 98.36 86.58 67.31 95.05 75.00
enable_checker 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
 i_tlul_adapter_reg 97.32 99.00 97.73 93.33 96.55 100.00
rv_dm_regs_csr_assert 100.00 100.00
 tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 100.00 100.00 100.00 100.00
tlul_assert_device_regs 99.65 100.00 100.00 98.95
tlul_assert_host_sba 94.30 100.00 85.71 97.18
 u_dm_top 87.42 90.14 73.26 92.86 80.84 100.00
 u_lc_en_sync_copies 100.00 100.00 100.00
 u_pm_en_sync 100.00 100.00 100.00 100.00
 u_prim_clock_mux2 85.19 100.00 55.56 100.00
 u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
 u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
 u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
 u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
 u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
 u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
 u_prim_rst_n_mux2 85.19 100.00 55.56 100.00
 u_reg_regs 98.32 98.69 99.35 93.55 100.00 100.00
 u_tlul_lc_gate_rom 94.64 100.00 100.00 85.71 100.00 87.50
 u_tlul_lc_gate_sba 81.96 94.49 84.00 57.14 86.67 87.50