Unified Coverage Report :: Module :: dm_csrs

Module : dm_csrs

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.52	84.12	61.33			54.12

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_csrs	66.52	84.12	61.33			54.12

---

Module Instance : tb.dut.u_dm_top.i_dm_csrs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.52	84.12	61.33			54.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.48	86.08	66.67			61.17	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_dm_top

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_fifo	93.06	100.00	77.78			94.44	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : dm_csrs

	Line No.	Total	Covered	Percent
TOTAL		277	233	84.12
CONT_ASSIGN	90	1	1	100.00
ALWAYS	107	7	7	100.00
ALWAYS	120	8	8	100.00
ALWAYS	137	8	8	100.00
ALWAYS	153	4	4	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
ALWAYS	204	2	0	0.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
ALWAYS	228	173	131	75.72
ALWAYS	568	6	6	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	581	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	611	46	46	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
90	1	1
107	1	1
108	1	1
109	1	1
110	1	1
111	1	1
112	1	1
113	1	1
			==> MISSING_ELSE
120	1	1
121	1	1
122	1	1
124	1	1
125	1	1
127	1	1
129	1	1
130	1	1
			==> MISSING_ELSE
137	1	1
138	1	1
139	1	1
141	1	1
142	1	1
144	1	1
146	1	1
147	1	1
			==> MISSING_ELSE
153	1	1
154	1	1
155	1	1
157	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
189	1	1
195	1	1
196	1	1
197	1	1
199	1	1
200	1	1
204	0	1
205	0	1
215	1	1
217	1	1
221	1	1
228	1	1
229	1	1
231	1	1
233	1	1
235	1	1
236	1	1
238	1	1
239	1	1
241	1	1
242	1	1
246	1	1
247	1	1
251	1	1
252	1	1
254	1	1
255	1	1
258	1	1
259	1	1
260	1	1
261	1	1
262	1	1
265	1	1
266	1	1
269	1	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
288	1	1
289	1	1
292	1	1
293	1	1
295	1	1
296	1	1
298	1	1
301	1	1
302	1	1
303	0	1
			MISSING_ELSE
307	1	1
308	1	1
309	0	1
310	1	1
311	0	1
312	0	1
313	0	1
315	1	1
316	1	1
319	1	1
323	1	1
324	1	1
325	0	1
			MISSING_ELSE
329	0	1
330	0	1
331	0	1
332	0	1
334	1	1
337	0	1
340	0	1
344	1	1
345	0	1
346	0	1
348	1	1
349	1	1
354	0	1
355	0	1
356	0	1
358	0	1
			MISSING_ELSE
366	1	1
367	1	1
369	1	1
371	1	1
372	1	1
374	1	1
377	1	1
378	1	1
379	0	1
			MISSING_ELSE
			==> MISSING_ELSE
385	1	1
387	1	1
388	0	1
			MISSING_ELSE
391	0	1
392	0	1
399	1	1
401	1	1
402	0	1
404	1	1
405	1	1
406	0	1
			MISSING_ELSE
412	1	1
413	1	1
414	1	1
418	1	1
419	1	1
420	0	1
			MISSING_ELSE
424	0	1
427	1	1
428	1	1
429	1	1
430	1	1
432	1	1
433	1	1
434	0	1
			MISSING_ELSE
440	1	1
441	1	1
446	1	1
449	1	1
450	1	1
451	1	1
			MISSING_ELSE
457	1	1
458	0	1
459	0	1
461	1	1
462	1	1
464	1	1
465	1	1
470	1	1
471	0	1
472	0	1
474	1	1
475	1	1
480	0	1
481	0	1
482	0	1
484	0	1
489	1	1
490	0	1
491	0	1
493	1	1
494	1	1
499	0	1
500	0	1
501	0	1
503	0	1
			MISSING_ELSE
510	1	1
511	1	1
			MISSING_ELSE
515	1	1
516	1	1
			MISSING_ELSE
520	1	1
521	0	1
			MISSING_ELSE
527	1	1
528	1	1
			MISSING_ELSE
531	1	1
532	1	1
			MISSING_ELSE
537	1	1
539	1	1
540	1	1
541	1	1
542	1	1
543	1	1
545	1	1
546	1	1
547	1	1
			MISSING_ELSE
549	1	1
550	1	1
			MISSING_ELSE
554	1	1
556	1	1
557	1	1
558	1	1
559	1	1
560	1	1
561	1	1
562	1	1
563	1	1
568	1	1
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
			==> MISSING_ELSE
578	1	1
579	1	1
580	1	1
581	1	1
582	1	1
584	1	1
587	1	1
611	1	1
612	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
619	1	1
620	1	1
621	1	1
622	1	1
623	1	1
625	1	1
627	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
652	1	1
653	1	1
654	1	1
655	1	1
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
661	1	1

---

Cond Coverage for Module : dm_csrs

	Total	Covered	Percent
Conditions	75	46	61.33
Logical	75	46	61.33
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (halted_aligned[selected_hart] & ((~unavailable_aligned[selected_hart])))
             --------------1--------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T12,T13
1	1	Covered	T7,T8,T9

 LINE       252
 EXPRESSION (halted_aligned[selected_hart] & ((~unavailable_aligned[selected_hart])))
             --------------1--------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T12,T13
1	1	Covered	T7,T8,T9

 LINE       254
 EXPRESSION (((~halted_aligned[selected_hart])) & ((~unavailable_aligned[selected_hart])))
             -----------------1----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T30,T26
1	1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (((~halted_aligned[selected_hart])) & ((~unavailable_aligned[selected_hart])))
             -----------------1----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T30,T26
1	1	Covered	T1,T2,T3

 LINE       292
 EXPRESSION (dmi_req_ready_o && dmi_req_valid_i && (dtm_op == DTM_READ))
             -------1-------    -------2-------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T7,T8

 LINE       292
 SUB-EXPRESSION (dtm_op == DTM_READ)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       302
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T15,T31,T25
1	Not Covered

 LINE       324
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T15,T31,T25
1	Not Covered

 LINE       344
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Not Covered
1	0	Not Covered

 LINE       348
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T32,T33,T34

 LINE       354
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       366
 EXPRESSION (dmi_req_ready_o && dmi_req_valid_i && (dtm_op == DTM_WRITE))
             -------1-------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T7,T8
1	1	1	Covered	T1,T2,T3

 LINE       366
 SUB-EXPRESSION (dtm_op == DTM_WRITE)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T15,T31,T25
1	Not Covered

 LINE       405
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T15,T31,T25
1	Not Covered

 LINE       419
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T14,T15,T22
1	Not Covered

 LINE       433
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T15,T31,T25
1	Not Covered

 LINE       450
 EXPRESSION (cmderr_q == CmdErrNone)
            ------------1-----------

-1-	Status	Tests
0	Covered	T14,T31,T25
1	Covered	T14,T15,T31

 LINE       464
 EXPRESSION (sbcs_q.sbbusyerror & ((~sbcs.sbbusyerror)))
             ---------1--------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Not Covered
1	1	Not Covered

 LINE       465
 EXPRESSION (((|sbcs.sberror)) ? 3'b0 : sbcs_q.sberror)
             --------1--------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T33,T35

 LINE       470
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Not Covered
1	0	Not Covered

 LINE       475
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T32,T33,T34

 LINE       480
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       489
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Not Covered
1	0	Not Covered

 LINE       494
 EXPRESSION (sbcs_q.sberror == '0)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T32,T33,T34

 LINE       499
 EXPRESSION (sbbusy_i || sbcs_q.sbbusyerror)
             ----1---    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       546
 EXPRESSION (((!dmcontrol_q.resumereq)) && dmcontrol_d.resumereq)
             -------------1------------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T9,T16

 LINE       549
 EXPRESSION (dmcontrol_q.resumereq && resumeack_i)
             ----------1----------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T16
1	0	Covered	T8,T9,T16
1	1	Covered	T8,T9,T16

 LINE       625
 EXPRESSION (SelectableHarts & havereset_d)
             -------1-------   -----2-----

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Covered	T1,T2,T3

---

Branch Coverage for Module : dm_csrs

	Line No.	Total	Covered	Percent
Branches		85	46	54.12
IF	112	2	1	50.00
IF	129	2	1	50.00
IF	146	2	1	50.00
IF	292	26	10	38.46
IF	366	34	16	47.06
IF	510	2	2	100.00
IF	515	2	2	100.00
IF	520	2	1	50.00
IF	527	2	2	100.00
IF	531	2	2	100.00
IF	546	2	2	100.00
IF	549	2	2	100.00
IF	572	2	1	50.00
IF	611	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_csrs.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	112	if ((hartsel_idx0 < 15'((((NrHarts - 1) / (2 ** 5)) + 1))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	129	if ((hartsel_idx1 < 10'((((NrHarts - 1) / (2 ** 10)) + 1))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	146	if ((hartsel_idx2 < 5'((((NrHarts - 1) / (2 ** 15)) + 1))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	292	if (((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == DTM_READ)))
-2-:	293	case (dm_csr_addr)
-3-:	296	if ((!cmdbusy_i))
-4-:	302	if ((cmderr_q == CmdErrNone))
-5-:	316	if ((!cmdbusy_i))
-6-:	324	if ((cmderr_q == CmdErrNone))
-7-:	344	if ((sbbusy_i || sbcs_q.sbbusyerror))
-8-:	354	if ((sbbusy_i || sbcs_q.sbbusyerror))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	Data0 DataEnd	1	-	-	-	-	-	Covered	T9,T36,T20
1	Data0 DataEnd	0	1	-	-	-	-	Not Covered
1	Data0 DataEnd	0	0	-	-	-	-	Covered	T15,T31,T25
1	DMControl	-	-	-	-	-	-	Covered	T1,T19,T25
1	DMStatus	-	-	-	-	-	-	Covered	T1,T8,T30
1	Hartinfo	-	-	-	-	-	-	Not Covered
1	AbstractCS	-	-	-	-	-	-	Covered	T7,T9,T12
1	AbstractAuto	-	-	-	-	-	-	Not Covered
1	Command	-	-	-	-	-	-	Not Covered
1	NextDM	-	-	-	-	-	-	Not Covered
1	ProgBuf0 ProgBufEnd	-	-	1	-	-	-	Covered	T1,T9,T19
1	ProgBuf0 ProgBufEnd	-	-	0	1	-	-	Not Covered
1	ProgBuf0 ProgBufEnd	-	-	0	0	-	-	Covered	T15,T31,T25
1	HaltSum0	-	-	-	-	-	-	Not Covered
1	HaltSum1	-	-	-	-	-	-	Not Covered
1	HaltSum2	-	-	-	-	-	-	Not Covered
1	HaltSum3	-	-	-	-	-	-	Not Covered
1	SBCS	-	-	-	-	-	-	Covered	T32,T33,T34
1	SBAddress0	-	-	-	-	-	-	Not Covered
1	SBAddress1	-	-	-	-	-	-	Not Covered
1	SBData0	-	-	-	-	1	-	Not Covered
1	SBData0	-	-	-	-	0	-	Covered	T32,T33,T34
1	SBData1	-	-	-	-	-	1	Not Covered
1	SBData1	-	-	-	-	-	0	Not Covered
1	default	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	if (((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == DTM_WRITE)))
-2-:	367	case (dm_csr_addr)
-3-:	369	if ((dm::DataCount > 4'b0))
-4-:	371	if ((!cmdbusy_i))
-5-:	378	if ((cmderr_q == CmdErrNone))
-6-:	387	if (dmcontrol_d.ackhavereset)
-7-:	401	if ((!cmdbusy_i))
-8-:	405	if ((cmderr_q == CmdErrNone))
-9-:	412	if ((!cmdbusy_i))
-10-:	419	if ((cmderr_q == CmdErrNone))
-11-:	427	if ((!cmdbusy_i))
-12-:	433	if ((cmderr_q == CmdErrNone))
-13-:	440	if ((!cmdbusy_i))
-14-:	450	if ((cmderr_q == CmdErrNone))
-15-:	457	if (sbbusy_i)
-16-:	465	((|sbcs.sberror)) ? 
-17-:	470	if ((sbbusy_i || sbcs_q.sbbusyerror))
-18-:	480	if ((sbbusy_i || sbcs_q.sbbusyerror))
-19-:	489	if ((sbbusy_i || sbcs_q.sbbusyerror))
-20-:	499	if ((sbbusy_i || sbcs_q.sbbusyerror))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests
1	Data0 DataEnd	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T36,T37
1	Data0 DataEnd	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	Data0 DataEnd	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T31,T25
1	Data0 DataEnd	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	DMControl	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	DMControl	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	DMStatus	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	Hartinfo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	AbstractCS	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	AbstractCS	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	AbstractCS	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T31,T25
1	Command	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T9,T12
1	Command	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
1	Command	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T22
1	NextDM	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
1	AbstractAuto	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T7,T9,T12
1	AbstractAuto	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	-	-	Not Covered
1	AbstractAuto	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	-	-	Covered	T15,T31,T25
1	ProgBuf0 ProgBufEnd	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T7,T9
1	ProgBuf0 ProgBufEnd	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T14,T15,T31
1	ProgBuf0 ProgBufEnd	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T14,T31,T25
1	SBCS	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
1	SBCS	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Covered	T33,T35
1	SBCS	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T32,T33,T34
1	SBAddress0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
1	SBAddress0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T32,T33,T34
1	SBAddress1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
1	SBAddress1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
1	SBData0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
1	SBData0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T32,T33,T34
1	SBData1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
1	SBData1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	510	if (cmderror_valid_i)

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	if (data_valid_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	if (ndmreset_ack_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	527	if (sberror_valid_i)

Branches:

-1-	Status	Tests
1	Covered	T33,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	531	if (sbdata_valid_i)

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	546	if (((!dmcontrol_q.resumereq) && dmcontrol_d.resumereq))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	if ((dmcontrol_q.resumereq && resumeack_i))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	572	if ((selected_hart <= 1'((NrHarts - 1))))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	611	if ((!rst_ni))
-2-:	627	if ((!dmcontrol_q.dmactive))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3