Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_csrs.i_fifo	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.93	100.00	85.29			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
70.19	86.64	62.67			61.25		i_dm_csrs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T3 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T37
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	53568015	21776	0	0
DataKnown_AKnownEnable	53568015	53088707	0	0
DepthKnown_A	53568015	53088707	0	0
RvalidKnown_A	53568015	53088707	0	0
WreadyKnown_A	53568015	53088707	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	53568015	21776	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	21776	0	0
T1	10625	7	0	0
T2	11112	9	0	0
T3	26803	11	0	0
T6	8131	4	0	0
T12	7468	12	0	0
T17	20064	6	0	0
T23	14278	5	0	0
T48	6490	1	0	0
T49	50558	21	0	0
T50	3291	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	21776	0	0
T1	10625	7	0	0
T2	11112	9	0	0
T3	26803	11	0	0
T6	8131	4	0	0
T12	7468	12	0	0
T17	20064	6	0	0
T23	14278	5	0	0
T48	6490	1	0	0
T49	50558	21	0	0
T50	3291	1	0	0

Line Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T3 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T37
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	53568015	21776	0	0
DataKnown_AKnownEnable	53568015	53088707	0	0
DepthKnown_A	53568015	53088707	0	0
RvalidKnown_A	53568015	53088707	0	0
WreadyKnown_A	53568015	53088707	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	53568015	21776	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	21776	0	0
T1	10625	7	0	0
T2	11112	9	0	0
T3	26803	11	0	0
T6	8131	4	0	0
T12	7468	12	0	0
T17	20064	6	0	0
T23	14278	5	0	0
T48	6490	1	0	0
T49	50558	21	0	0
T50	3291	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	53088707	0	0
T1	10625	10422	0	0
T2	11112	11015	0	0
T3	26803	26403	0	0
T6	8131	5266	0	0
T12	7468	7350	0	0
T17	20064	19738	0	0
T23	14278	14089	0	0
T48	6490	6141	0	0
T49	50558	45374	0	0
T50	3291	3005	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	53568015	21776	0	0
T1	10625	7	0	0
T2	11112	9	0	0
T3	26803	11	0	0
T6	8131	4	0	0
T12	7468	12	0	0
T17	20064	6	0	0
T23	14278	5	0	0
T48	6490	1	0	0
T49	50558	21	0	0
T50	3291	1	0	0