Line Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| ALWAYS | 133 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
| ALWAYS | 169 | 0 | 0 | |
| ALWAYS | 179 | 0 | 0 | |
94 // bits set. For writes the supplied be_i is used as the mask.
95 1/1 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
Tests: T1 T2 T3
96
97 1/1 assign tl_out = '{
Tests: T1 T2 T3
98 a_valid: req_i,
99 a_opcode: (~we_i) ? Get :
100 (&be_i) ? PutFullData :
101 PutPartialData,
102 a_param: 3'h0,
103 a_size: top_pkg::TL_SZW'(WordSize),
104 a_mask: tl_be,
105 a_source: tl_source,
106 a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
107 a_data: wdata_i,
108 a_user: '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i, rsvd: user_rsvd_i},
109 d_ready: 1'b1
110 };
111
112 tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
113 .tl_i(tl_out),
114 .tl_o(tl_o)
115 );
116
117 1/1 assign gnt_o = tl_i.a_ready;
Tests: T1 T2 T3
118
119 1/1 assign valid_o = tl_i.d_valid;
Tests: T1 T2 T3
120 1/1 assign rdata_o = tl_i.d_data;
Tests: T1 T2 T3
121 1/1 assign rdata_intg_o = tl_i.d_user.data_intg;
Tests: T1 T2 T3
122
123 logic intg_err;
124 tlul_rsp_intg_chk #(
125 .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
126 ) u_rsp_chk (
127 .tl_i,
128 .err_o(intg_err)
129 );
130
131 logic intg_err_q;
132 always_ff @(posedge clk_i or negedge rst_ni) begin
133 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
134 1/1 intg_err_q <= '0;
Tests: T1 T2 T3
135 1/1 end else if (intg_err) begin
Tests: T1 T2 T3
136 1/1 intg_err_q <= 1'b1;
Tests: T40 T115 T20
137 end
MISSING_ELSE
138 end
139
140 // err_o is transactional. This allows the host to continue
141 // debug without receiving an endless stream of errors.
142 1/1 assign err_o = tl_i.d_error | intg_err;
Tests: T1 T2 T3
143
144 // intg_err_o is permanent once detected, and should be used
145 // to trigger alerts
146 1/1 assign intg_err_o = intg_err_q | intg_err;
Tests: T1 T2 T3
147
148 // Addresses are assumed to be word-aligned, and the bottom bits are ignored
149 logic unused_addr_bottom_bits;
150 1/1 assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
Tests: T1 T2 T3
151
152 // Explicitly ignore unused fields of tl_i
153 logic unused_tl_i_fields;
154 1/1 assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
Tests: T1 T2 T3
155 tl_i.d_size, tl_i.d_source, tl_i.d_sink,
156 tl_i.d_user};
157
158 `ifdef INC_ASSERT
159 //VCS coverage off
160 // pragma coverage off
161 localparam int OutstandingReqCntW =
162 (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
163 localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
164
165 logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
166 logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
167
168 always_comb begin
169 unreachable outstanding_reqs_d = outstanding_reqs_q;
170
171 unreachable if ((req_i && gnt_o) && !valid_o) begin
172 unreachable outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
173 unreachable end else if (!(req_i && gnt_o) && valid_o) begin
174 unreachable outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
175 end
==> MISSING_ELSE
176 end
177
178 always_ff @(posedge clk_i or negedge rst_ni) begin
179 unreachable if (!rst_ni) begin
180 unreachable outstanding_reqs_q <= '0;
181 end else begin
182 unreachable outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Module :
tlul_adapter_host
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 95
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 97
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T19,T40 |
| 1 | Covered | T19,T40,T183 |
LINE 142
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T49 |
| 0 | 1 | Covered | T40,T115,T20 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T40,T115,T20 |
| 1 | 0 | Covered | T40,T115,T20 |
Branch Coverage for Module :
tlul_adapter_host
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
| IF |
133 |
3 |
3 |
100.00 |
95 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T18,T19,T40 |
133 if (!rst_ni) begin
-1-
134 intg_err_q <= '0;
==>
135 end else if (intg_err) begin
-2-
136 intg_err_q <= 1'b1;
==>
137 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T40,T115,T20 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
93960544 |
12734 |
0 |
0 |
| T6 |
8131 |
0 |
0 |
0 |
| T7 |
12071 |
0 |
0 |
0 |
| T12 |
7468 |
0 |
0 |
0 |
| T17 |
20064 |
1 |
0 |
0 |
| T18 |
0 |
63 |
0 |
0 |
| T19 |
0 |
86 |
0 |
0 |
| T23 |
14278 |
0 |
0 |
0 |
| T26 |
1849 |
0 |
0 |
0 |
| T40 |
0 |
14 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T48 |
6490 |
0 |
0 |
0 |
| T49 |
50558 |
0 |
0 |
0 |
| T50 |
3291 |
0 |
0 |
0 |
| T77 |
1068 |
0 |
0 |
0 |
| T81 |
0 |
1 |
0 |
0 |
| T84 |
0 |
76 |
0 |
0 |
| T85 |
0 |
1 |
0 |
0 |
| T115 |
0 |
14 |
0 |
0 |
| T184 |
0 |
6 |
0 |
0 |
