Unified Coverage Report :: Module :: prim_blanker

Module : prim_blanker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_blanker_0/rtl/prim_blanker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d
tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d
tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_h2d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.72	72.55	33.33		28.57	54.17	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[0].u_prim_blanker_d2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.72	72.55	33.33		28.57	54.17	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_h2d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.72	72.55	33.33		28.57	54.17	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.gen_lc_gating_muxes[1].u_prim_blanker_d2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
47.72	72.55	33.33		28.57	54.17	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_h2d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.72	96.08	77.78		71.43	83.33	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[0].u_prim_blanker_d2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.72	96.08	77.78		71.43	83.33	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_h2d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.72	96.08	77.78		71.43	83.33	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.gen_lc_gating_muxes[1].u_prim_blanker_d2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.72	96.08	77.78		71.43	83.33	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_blank_and	100.00	100.00