Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp	100.00	100.00	100.00			100.00
tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
82.25	86.27	76.47		100.00	81.82	66.67	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	38	14	14	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	73	1	1	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
40         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
41         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
42         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
43         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
44         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
45         1/1                err_rsp_pending <= 1'b0;
           Tests:       T17 T105 T45 
46         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
47         1/1                err_rsp_pending <= 1'b1;
           Tests:       T17 T105 T45 
48         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T17 T105 T45 
49         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T17 T105 T45 
50         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T17 T105 T45 
51         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T17 T105 T45 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
56         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
57                        if (ReturnBlankResp) begin : gen_zero_resp
58                          assign tl_h_o_int.d_data = '0;
59                        end else begin : gen_err_resp
60         1/1              assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
61                                                                                                  DataWhenError;
62                        end
63         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
64                        assign tl_h_o_int.d_sink   = '0;
65                        assign tl_h_o_int.d_param  = '0;
66         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
67         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
68                        assign tl_h_o_int.d_user   = '0;
69                        assign tl_h_o_int.d_error  = ~ReturnBlankResp;
70                      
71                        // Waive unused bits of tl_h_i
72                        logic unused_tl_h;
73         1/1            assign unused_tl_h = ^{tl_h_i, err_instr_type};
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37
1	1	Covered	T17,T105,T45

 LINE       46
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37
1	1	Covered	T17,T105,T45

 LINE       67
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T105,T184,T62
1	Covered	T1,T2,T3

 LINE       67
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	67	2	2	100.00
IF	38	4	4	100.00

67           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T105,T184,T62

38             if (!rst_ni) begin
               -1-  
39               err_rsp_pending <= 1'b0;
                 ==>
40               err_source      <= {top_pkg::TL_AIW{1'b0}};
41               err_opcode      <= Get;
42               err_size        <= '0;
43               err_instr_type  <= MuBi4False;
44             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
45               err_rsp_pending <= 1'b0;
                 ==>
46             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
47               err_rsp_pending <= 1'b1;
                 ==>
48               err_source      <= tl_h_i.a_source;
49               err_opcode      <= tl_h_i.a_opcode;
50               err_size        <= tl_h_i.a_size;
51               err_instr_type  <= tl_h_i.a_user.instr_type;
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T105,T45
0	0	1	Covered	T17,T105,T45
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	38	14	14	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	73	1	1	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
40         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
41         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
42         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
43         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
44         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
45         1/1                err_rsp_pending <= 1'b0;
           Tests:       T17 T45 T184 
46         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
47         1/1                err_rsp_pending <= 1'b1;
           Tests:       T17 T45 T184 
48         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T17 T45 T184 
49         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T17 T45 T184 
50         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T17 T45 T184 
51         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T17 T45 T184 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
56         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
57                        if (ReturnBlankResp) begin : gen_zero_resp
58                          assign tl_h_o_int.d_data = '0;
59                        end else begin : gen_err_resp
60         1/1              assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
61                                                                                                  DataWhenError;
62                        end
63         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
64                        assign tl_h_o_int.d_sink   = '0;
65                        assign tl_h_o_int.d_param  = '0;
66         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
67         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
68                        assign tl_h_o_int.d_user   = '0;
69                        assign tl_h_o_int.d_error  = ~ReturnBlankResp;
70                      
71                        // Waive unused bits of tl_h_i
72                        logic unused_tl_h;
73         1/1            assign unused_tl_h = ^{tl_h_i, err_instr_type};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T17,T45,T184

 LINE       46
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T17,T45,T184

 LINE       67
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T184
1	Covered	T1,T2,T3

 LINE       67
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	67	2	2	100.00
IF	38	4	4	100.00

67           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T184

38             if (!rst_ni) begin
               -1-  
39               err_rsp_pending <= 1'b0;
                 ==>
40               err_source      <= {top_pkg::TL_AIW{1'b0}};
41               err_opcode      <= Get;
42               err_size        <= '0;
43               err_instr_type  <= MuBi4False;
44             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
45               err_rsp_pending <= 1'b0;
                 ==>
46             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
47               err_rsp_pending <= 1'b1;
                 ==>
48               err_source      <= tl_h_i.a_source;
49               err_opcode      <= tl_h_i.a_opcode;
50               err_size        <= tl_h_i.a_size;
51               err_instr_type  <= tl_h_i.a_user.instr_type;
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T45,T184
0	0	1	Covered	T17,T45,T184
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	38	14	14	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	73	1	1	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
40         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
41         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
42         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
43         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
44         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
45         1/1                err_rsp_pending <= 1'b0;
           Tests:       T17 T105 T85 
46         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
47         1/1                err_rsp_pending <= 1'b1;
           Tests:       T17 T105 T85 
48         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T17 T105 T85 
49         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T17 T105 T85 
50         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T17 T105 T85 
51         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T17 T105 T85 
52                          end
                        MISSING_ELSE
53                        end
54                      
55         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
56         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
57                        if (ReturnBlankResp) begin : gen_zero_resp
58                          assign tl_h_o_int.d_data = '0;
59                        end else begin : gen_err_resp
60         1/1              assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
61                                                                                                  DataWhenError;
62                        end
63         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
64                        assign tl_h_o_int.d_sink   = '0;
65                        assign tl_h_o_int.d_param  = '0;
66         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
67         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
68                        assign tl_h_o_int.d_user   = '0;
69                        assign tl_h_o_int.d_error  = ~ReturnBlankResp;
70                      
71                        // Waive unused bits of tl_h_i
72                        logic unused_tl_h;
73         1/1            assign unused_tl_h = ^{tl_h_i, err_instr_type};
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T48,T49
1	0	Covered	T37
1	1	Covered	T17,T105,T85

 LINE       46
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37
1	1	Covered	T17,T105,T85

 LINE       67
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T105,T62,T37
1	Covered	T1,T2,T3

 LINE       67
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	67	2	2	100.00
IF	38	4	4	100.00

67           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T105,T62,T37

38             if (!rst_ni) begin
               -1-  
39               err_rsp_pending <= 1'b0;
                 ==>
40               err_source      <= {top_pkg::TL_AIW{1'b0}};
41               err_opcode      <= Get;
42               err_size        <= '0;
43               err_instr_type  <= MuBi4False;
44             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
45               err_rsp_pending <= 1'b0;
                 ==>
46             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
47               err_rsp_pending <= 1'b1;
                 ==>
48               err_source      <= tl_h_i.a_source;
49               err_opcode      <= tl_h_i.a_opcode;
50               err_size        <= tl_h_i.a_size;
51               err_instr_type  <= tl_h_i.a_user.instr_type;
52             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T105,T85
0	0	1	Covered	T17,T105,T85
0	0	0	Covered	T1,T2,T3