Unified Coverage Report :: Module :: prim_generic_flop_2sync

Module : prim_generic_flop_2sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_flop_2sync_0/rtl/prim_generic_flop_2sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_pm_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic
tb.dut.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic
tb.dut.u_prim_flop_2sync_lc_rst_sync.gen_generic.u_impl_generic
tb.dut.dap.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic
tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic
tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic
tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_pm_en_sync.gen_flops.u_prim_flop_2sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.u_prim_flop_2sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_flop_2sync_lc_rst_assert.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_2sync_lc_rst_assert

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_flop_2sync_lc_rst_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_flop_2sync_lc_rst_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_combined_rstn_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rz_hs_protocol.ack_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rz_hs_protocol.req_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rz_hs_protocol.ack_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rz_hs_protocol.req_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_1	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00