Unified Coverage Report :: Module

Module : debug_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.55	89.30	72.41		100.00	88.46		i_dm_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : debug_rom

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	3	3	100.00
ALWAYS	66	3	3	100.00



52                      
53         1/1            assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q;
           Tests:       T1 T2 T3 
54                      
55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                addr_q <= '0;
           Tests:       T1 T2 T3 
58                          end else begin
59         1/1                addr_q <= addr_d;
           Tests:       T1 T2 T3 
60                          end
61                        end
62                      
63                        // this prevents spurious Xes from propagating into
64                        // the speculative fetch stage of the core
65                        always_comb begin : p_outmux
66         1/1              rdata_o = '0;
           Tests:       T1 T2 T3 
67         1/1              if (addr_q < $clog2(RomSize)'(RomSize)) begin
           Tests:       T1 T2 T3 
68         1/1                rdata_o = mem[addr_q];
           Tests:       T1 T2 T3 
69                          end
                        MISSING_ELSE

Cond Coverage for Module : debug_rom

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (req_i ? addr_i[(($clog2(RomSize) - 1) + 3):3] : addr_q)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T12

Branch Coverage for Module : debug_rom

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	53	2	2	100.00
IF	56	2	2	100.00
IF	67	2	2	100.00



53           assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q;
                                   -1-  
                                   ==>  
                                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               addr_q <= '0;
                 ==>
58             end else begin
59               addr_q <= addr_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



67             if (addr_q < $clog2(RomSize)'(RomSize)) begin
               -1-  
68               rdata_o = mem[addr_q];
                 ==>
69             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T62,T36,T34