Unified Coverage Report :: Module :: prim_secded_inv_64_57_enc

Module : prim_secded_inv_64_57_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen	100.00	100.00
tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen	100.00	100.00
tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.u_cmd_gen	100.00	100.00
tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen	100.00	100.00
tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen	100.00	100.00

---

Module Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_rsp_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.u_cmd_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_cmd_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_rsp_intg_gen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_secded_inv_64_57_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.u_cmd_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 64'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[57] = ^(data_o & 64'h0103FFF800007FFF);
           Tests:       T1 T2 T3 
15         1/1              data_o[58] = ^(data_o & 64'h017C1FF801FF801F);
           Tests:       T1 T2 T3 
16         1/1              data_o[59] = ^(data_o & 64'h01BDE1F87E0781E1);
           Tests:       T1 T2 T3 
17         1/1              data_o[60] = ^(data_o & 64'h01DEEE3B8E388E22);
           Tests:       T1 T2 T3 
18         1/1              data_o[61] = ^(data_o & 64'h01EF76CDB2C93244);
           Tests:       T1 T2 T3 
19         1/1              data_o[62] = ^(data_o & 64'h01F7BB56D5525488);
           Tests:       T1 T2 T3 
20         1/1              data_o[63] = ^(data_o & 64'h01FBDDA769A46910);
           Tests:       T1 T2 T3 
21         1/1              data_o ^= 64'h5400000000000000;
           Tests:       T1 T2 T3