RV_TIMER Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	34.947m	687.241ms	193	200	96.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.640s	16.199us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.670s	19.304us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.840s	3.119ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	59.924us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.540s	487.298us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.670s	19.304us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	59.924us	5	5	100.00
V1		TOTAL			248	255	97.25
V2	random_reset	rv_timer_random_reset	20.001m	201.344ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.383m	814.298ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	13.835m	465.593ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	13.835m	465.593ms	50	50	100.00
V2	stress	rv_timer_stress_all	1.676h	7.490s	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.610s	48.511us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.160s	385.606us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.160s	385.606us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.640s	16.199us	5	5	100.00
		rv_timer_csr_rw	0.670s	19.304us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	59.924us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	143.808us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.640s	16.199us	5	5	100.00
		rv_timer_csr_rw	0.670s	19.304us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	59.924us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	143.808us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	256.534us	5	5	100.00
		rv_timer_tl_intg_err	1.460s	123.418us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.460s	123.418us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	28.324m	131.597ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			610	620	98.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.38	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:

Test rv_timer_random has 6 failures.

4.rv_timer_random.4157769379
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.rv_timer_random.845730465
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test rv_timer_disabled has 2 failures.

9.rv_timer_disabled.1436845207
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.rv_timer_disabled.3100090481
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/36.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_stress_all has 1 failures.

34.rv_timer_stress_all.3104696405
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 175.rv_timer_random.1834460589
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/175.rv_timer_random/latest/run.log
```
  Job ID: smart:79013c55-ba01-4a32-b36e-9939e9768757
```