RV_TIMER Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	53.391m	616.763ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.570s	15.274us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	12.250us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.280s	89.747us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.800s	61.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.580s	91.906us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	12.250us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	61.899us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	28.951m	244.627ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.250m	737.667ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	14.607m	1.407s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	14.607m	1.407s	50	50	100.00
V2	stress	rv_timer_stress_all	1.915h	3.941s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.620s	30.515us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.220s	65.224us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.220s	65.224us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.570s	15.274us	5	5	100.00
		rv_timer_csr_rw	0.610s	12.250us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	61.899us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	20.326us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.570s	15.274us	5	5	100.00
		rv_timer_csr_rw	0.610s	12.250us	20	20	100.00
		rv_timer_csr_aliasing	0.800s	61.899us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	20.326us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.960s	170.221us	5	5	100.00
		rv_timer_tl_intg_err	1.460s	124.820us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.460s	124.820us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	29.678m	126.263ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			618	620	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.36	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test rv_timer_csr_mem_rw_with_rand_reset has 1 failures.

9.rv_timer_csr_mem_rw_with_rand_reset.90390548897265637863851045821220549479739546255508429010952225185285877814629
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest/run.log

  [make]: simulate
  cd /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679761253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.679761253
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Dec 27 13:09 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rv_timer_random_reset has 1 failures.
  - 43.rv_timer_random_reset.74473326032791110502789858432006589605369190953851335987837072097321890547573
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```