70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 40.649m | 117.178ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 30.461us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.680s | 41.198us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.510s | 4.625ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 115.644us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.430s | 56.627us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.680s | 41.198us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 115.644us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 9.819m | 282.062ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.811m | 740.463ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 26.639m | 6.501s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 26.639m | 6.501s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.972h | 3.052s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 26.779us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.990s | 332.628us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.990s | 332.628us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 30.461us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.680s | 41.198us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 115.644us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 562.433us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 30.461us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.680s | 41.198us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 115.644us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.870s | 562.433us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.900s | 1.124ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.530s | 147.795us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.530s | 147.795us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 19.681m | 454.993ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 582 | 620 | 93.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.53 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.09 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
0.rv_timer_stress_all_with_rand_reset.47677097420888718091385990525643470916950721884750477581153979113272844258714
Line 333, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 81587137473 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 81587137473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.92770749845770049913454038437656988535988508609934989941395395193130619813682
Line 743, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 48653287891 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 48653287891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
13.rv_timer_disabled.85373269386257164581711921116710555922940869766441932389606137939840512614765
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/13.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.rv_timer_disabled.102812862067188220482520185863696975431237518021815725641371840840779239332372
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.