RV_TIMER Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	43.928m	1.822s	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.570s	16.805us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.700s	17.338us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.760s	282.787us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.750s	26.085us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.110s	25.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.700s	17.338us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	26.085us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	52.631m	441.373ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.597m	803.390ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	26.055m	6.877s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	26.055m	6.877s	50	50	100.00
V2	stress	rv_timer_stress_all	44.916m	3.006s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.580s	51.315us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.810s	711.935us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.810s	711.935us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.570s	16.805us	5	5	100.00
		rv_timer_csr_rw	0.700s	17.338us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	26.085us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	181.003us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.570s	16.805us	5	5	100.00
		rv_timer_csr_rw	0.700s	17.338us	20	20	100.00
		rv_timer_csr_aliasing	0.750s	26.085us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	181.003us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.850s	90.088us	5	5	100.00
		rv_timer_tl_intg_err	1.400s	426.164us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.400s	426.164us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	15.704m	96.018ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			574	620	92.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.36	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:
- Test rv_timer_stress_all_with_rand_reset has 42 failures.
  - 0.rv_timer_stress_all_with_rand_reset.100531264144396948190482552170499711051998842852585248796083442386449008787000
    Line 780, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96017582420 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10016 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 96017582420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.60171504320431243575423209313943087349999216378543566587537403835619210729655
    Line 600, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 80459371913 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10032 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 80459371913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 40 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_random_reset has 1 failures.
  - 35.rv_timer_random_reset.85053088283398674783027910551406088376777205185654978140020968392135496532091
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/35.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 1 failures.
  - 39.rv_timer_disabled.104011392781019943968372771951119681980918115528117287796258797278199184968846
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 8.rv_timer_stress_all_with_rand_reset.71310782196957395418161686301521084287259788197046013025822301122967818520390
    Line 409, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 190615145195 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 190615145195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 159.rv_timer_random.7151300647982255053049929621228660137473604611971153780210329463846677816287
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/159.rv_timer_random/latest/run.log
```
  Job ID: smart:5c82c7cc-70e3-47f0-9df0-3520fe1bac03
```

RV_TIMER Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e844018f2c`