bc285b7382| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 59.395m | 416.128ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 53.254us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 25.919us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.610s | 370.871us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.850s | 49.075us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.360s | 29.876us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 25.919us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.850s | 49.075us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 14.472m | 185.576ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.190m | 220.572ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 28.416m | 1.563s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 28.416m | 1.563s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.646h | 849.303ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 29.580us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.980s | 823.274us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.980s | 823.274us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 53.254us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 25.919us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 49.075us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 190.303us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 53.254us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 25.919us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 49.075us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 190.303us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.850s | 271.910us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.410s | 230.485us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.410s | 230.485us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 22.074m | 473.366ms | 10 | 50 | 20.00 |
| V3 | TOTAL | 10 | 50 | 20.00 | |||
| TOTAL | 578 | 620 | 93.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:827) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 40 failures:
0.rv_timer_stress_all_with_rand_reset.64042309271810309048940429670609966193810502108204444110968536990708613151968
Line 494, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21147908101 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10023 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21147908101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.2879856999986843785232897128239833550761371711937413906095727622658884892854
Line 514, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96985288056 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10037 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 96985288056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
5.rv_timer_disabled.71277086431419466179873028458643217397973883590851132516232900828276260294350
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_timer_disabled.38598999508504225597702743838605674810350799222310881121301387195432745743249
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/38.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---