c187a82ee8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 43.505m | 719.295ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.610s | 46.096us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.710s | 14.562us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.720s | 356.202us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 106.842us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.840s | 42.496us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.710s | 14.562us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.830s | 106.842us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 16.849m | 79.819ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.617m | 373.138ms | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 21.815m | 3.695s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 21.815m | 3.695s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.613h | 781.351ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.660s | 18.815us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.660s | 211.638us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.660s | 211.638us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.610s | 46.096us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.710s | 14.562us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 106.842us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 40.026us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.610s | 46.096us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.710s | 14.562us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 106.842us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 40.026us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.990s | 323.504us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.420s | 154.597us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.420s | 154.597us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 15.621m | 116.118ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:827) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
0.rv_timer_stress_all_with_rand_reset.89497339586043206480703975287349260445145092541712029091136515685434840481356
Line 900, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 247585639355 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10045 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 247585639355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.90328125955856531260141758908448137726446333651104135401422457949898153991603
Line 1187, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 58547520243 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 58547520243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
15.rv_timer_disabled.54988151717307034727483659450827741173744606420281766977749417402238613157057
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_timer_disabled.101698675956229578429048993934103832294308587513555703830290669641559443069123
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
111.rv_timer_random.55154783246305404350426801761608692696493419860879380433068967249507461405281
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/111.rv_timer_random/latest/run.log
Job ID: smart:963fa4de-4a2c-44f9-a7d4-039d8ed82a62