919341eb22| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 52.648m | 280.730ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 49.832us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 116.377us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.660s | 1.473ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.810s | 31.178us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.080s | 371.948us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 116.377us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.810s | 31.178us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 16.054m | 50.612ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.034m | 610.749ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 33.195m | 6.768s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 33.195m | 6.768s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 55.856m | 1.498s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.640s | 17.966us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.230s | 584.414us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.230s | 584.414us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 49.832us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 116.377us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 31.178us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 35.369us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 49.832us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 116.377us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.810s | 31.178us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 35.369us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.840s | 62.636us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.670s | 2.145ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.670s | 2.145ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 18.385m | 392.086ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
0.rv_timer_stress_all_with_rand_reset.69465968409570629473704148822602062399330027203903081896303253562446416888624
Line 464, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13418186891 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10016 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13418186891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.1172547222446347166894619664373644099674393719874408903788867162194476036001
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1674869283 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1674869283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
17.rv_timer_disabled.80739581577566379852263872251125874025690692685884185622419860924485860513710
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/17.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_timer_disabled.34455904810060157618752319146640758162190818176062598183340746604595722455873
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.