b111fbcef3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 37.236m | 138.455ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.640s | 80.037us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 73.139us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.740s | 1.101ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 121.124us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.770s | 133.641us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 73.139us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.830s | 121.124us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 24.261m | 167.089ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.473m | 191.812ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.725m | 742.089ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.725m | 742.089ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.406h | 1.924s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 14.755us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.900s | 238.579us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.900s | 238.579us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.640s | 80.037us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 73.139us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 121.124us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 70.986us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.640s | 80.037us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 73.139us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 121.124us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 70.986us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.940s | 313.744us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.500s | 393.806us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.500s | 393.806us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 24.400m | 212.952ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 583 | 620 | 94.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
0.rv_timer_stress_all_with_rand_reset.19681187622110977694014333090978757082472274889161627018932096089921682707943
Line 676, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55366711788 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 55366711788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.52463362211666698565710531468561956762259210746539907456123950970202197211878
Line 832, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66179484271 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 66179484271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
24.rv_timer_stress_all_with_rand_reset.3398471430566337499890470262779528525929794785188889170163316321153999028627
Line 1053, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 52248865321 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 52248865321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
43.rv_timer_disabled.113335908764074065607789640979635534151528853434097493205732807596336383682072
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---