1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 58.902m | 436.170ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.570s | 19.614us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.600s | 17.102us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.440s | 2.479ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 42.138us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.420s | 33.298us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.600s | 17.102us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 42.138us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 46.588m | 426.789ms | 48 | 50 | 96.00 |
| V2 | disabled | rv_timer_disabled | 5.521m | 198.899ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 35.354m | 9.378s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 35.354m | 9.378s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 59.751m | 1.904s | 49 | 50 | 98.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 31.679us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.800s | 342.115us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.800s | 342.115us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.570s | 19.614us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.600s | 17.102us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 42.138us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 113.131us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.570s | 19.614us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.600s | 17.102us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 42.138us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 113.131us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.020s | 902.885us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.490s | 448.079us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.490s | 448.079us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 22.014m | 198.378ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
1.rv_timer_stress_all_with_rand_reset.103290686502277566405918751199707544209484033155395920409810427889300546600990
Line 400, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26561289499 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 26561289499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.45201565407680138408607796126975299787353492250897285464113075178467650713230
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18260448954 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18260448954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_timer_random_reset has 2 failures.
5.rv_timer_random_reset.26632397275289724748038490901231041719210370145827315365257527384311277278702
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.rv_timer_random_reset.50515335739523136327436191306870615776058764104398287812640360579986000312255
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/40.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_stress_all has 1 failures.
5.rv_timer_stress_all.113159523376291689439726993816535978081785458270964302490510568402806354538408
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/5.rv_timer_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---