9656691e03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 47.871m | 1.086s | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.550s | 274.951us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 181.514us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.510s | 883.114us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.760s | 36.041us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.570s | 62.263us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 181.514us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.760s | 36.041us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 16.970m | 29.048ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.949m | 819.442ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 24.660m | 3.160s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 24.660m | 3.160s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.601h | 1.096s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 30.113us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.940s | 757.718us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.940s | 757.718us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.550s | 274.951us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 181.514us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 36.041us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 165.978us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.550s | 274.951us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 181.514us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 36.041us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 165.978us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 290 | 290 | 100.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.080s | 232.883us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.830s | 1.180ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.830s | 1.180ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 16.020m | 348.763ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 578 | 620 | 93.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 7 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
0.rv_timer_stress_all_with_rand_reset.66434108252876963386263033804025302531618484941984304125500831150331673633760
Line 270, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11925808559 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11925808559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.109157042425842163966226549961492640024955043746139761711363589300232807876927
Line 530, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 95640904750 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10012 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 95640904750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
42.rv_timer_random.6087879009231966688344917194669544828966937164811608980115714576354017334361
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_random/latest/run.log
Job ID: smart:99f999a7-e378-44b9-804f-505f53ccfe15