25e609d6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 49.903m | 458.023ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 17.467us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 147.346us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.610s | 610.701us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 127.373us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.650s | 299.760us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 147.346us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 127.373us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 20.606m | 697.443ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.849m | 1.000s | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 17.287m | 4.300s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 17.287m | 4.300s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 44.552m | 5.228s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 64.736us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.930s | 174.597us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.930s | 174.597us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 17.467us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 147.346us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 127.373us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 19.254us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 17.467us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 147.346us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 127.373us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 19.254us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.120s | 327.045us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.500s | 1.326ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.500s | 1.326ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 28.685m | 177.518ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.51 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.98 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
0.rv_timer_stress_all_with_rand_reset.73301439125658584976950686868634490709907235010819033847378945734869380848611
Line 388, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14412024635 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14412024635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.84052123796180812824881983495660801613750588251159257275793446046896064776704
Line 1025, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68922597381 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 68922597381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
8.rv_timer_disabled.61485434883212316902715954670385100517989649761385423724120974039124010213506
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---