6e698b4dfe| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 42.621m | 350.683ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 17.993us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.690s | 46.352us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.900s | 420.254us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.860s | 36.178us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.530s | 36.910us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.690s | 46.352us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.860s | 36.178us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 24.642m | 202.757ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.887m | 1.000s | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.250m | 3.679s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.250m | 3.679s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.202h | 572.159ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 17.310us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.100s | 352.570us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.100s | 352.570us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 17.993us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.690s | 46.352us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 36.178us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 99.871us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 17.993us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.690s | 46.352us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 36.178us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 99.871us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.950s | 105.682us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.470s | 804.040us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.470s | 804.040us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 15.064m | 392.295ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.63884819338957201204904979840602720859548208528182253789330972384553822393149
Line 868, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 78870631991 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 78870631991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.20068084733809631040794237196408005414203159659163507737977212588388064791858
Line 411, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13262246157 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13262246157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
2.rv_timer_disabled.85437441074256557202585811393181535211981331464639254441989935214658092333711
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_timer_disabled.62870201670979971627891461224781632461861952831525479887954150858669315509167
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:752) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
48.rv_timer_stress_all_with_rand_reset.577884777952761896529928367961219652629442583236166117156492446586935733536
Line 1089, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/48.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50853917649 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 50853917649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---