RV_TIMER Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 44.040m 212.291ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.620s 70.164us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.670s 37.616us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.650s 2.086ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.820s 32.645us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.510s 68.321us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.670s 37.616us 20 20 100.00
rv_timer_csr_aliasing 0.820s 32.645us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 25.944m 50.592ms 50 50 100.00
V2 disabled rv_timer_disabled 5.945m 863.177ms 48 50 96.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 20.954m 3.034s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 20.954m 3.034s 50 50 100.00
V2 stress rv_timer_stress_all 1.114h 2.851s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.620s 58.735us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.440s 1.400ms 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.440s 1.400ms 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.620s 70.164us 5 5 100.00
rv_timer_csr_rw 0.670s 37.616us 20 20 100.00
rv_timer_csr_aliasing 0.820s 32.645us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 34.125us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.620s 70.164us 5 5 100.00
rv_timer_csr_rw 0.670s 37.616us 20 20 100.00
rv_timer_csr_aliasing 0.820s 32.645us 5 5 100.00
rv_timer_same_csr_outstanding 0.840s 34.125us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err rv_timer_sec_cm 0.960s 284.805us 5 5 100.00
rv_timer_tl_intg_err 1.440s 105.583us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.440s 105.583us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 19.896m 214.731ms 11 50 22.00
V3 TOTAL 11 50 22.00
TOTAL 579 620 93.39

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.59 99.36 98.73 100.00 -- 100.00 100.00 99.43

Failure Buckets

Past Results