be1c4a4f52| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.040m | 212.291ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 70.164us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.670s | 37.616us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.650s | 2.086ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.820s | 32.645us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.510s | 68.321us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.670s | 37.616us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.820s | 32.645us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 25.944m | 50.592ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 5.945m | 863.177ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.954m | 3.034s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.954m | 3.034s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.114h | 2.851s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 58.735us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.440s | 1.400ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.440s | 1.400ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 70.164us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.670s | 37.616us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 32.645us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 34.125us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 70.164us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.670s | 37.616us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.820s | 32.645us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 34.125us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.960s | 284.805us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.440s | 105.583us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.440s | 105.583us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 19.896m | 214.731ms | 11 | 50 | 22.00 |
| V3 | TOTAL | 11 | 50 | 22.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.43 |
UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:
0.rv_timer_stress_all_with_rand_reset.81718752948144795271768269315272470384496704938755146128143117704190765382713
Line 405, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123612495254 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10042 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123612495254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.82998334790161248591352683435648269499411636305458329591244749413046349908774
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16235385971 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16235385971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 37 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
4.rv_timer_disabled.70163124299565475684999824989572124640986814718388466113697798803609913863686
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rv_timer_disabled.69123535549063818016158306127134881450319667530654555894339622913317277506120
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---